clock divider in VHDL - why is my code not working?

Discussion in 'Homework Help' started by keemnal, Mar 5, 2008.

  1. keemnal

    Thread Starter New Member

    Nov 12, 2007
    2
    0
    Hi,

    I have to generate 3 clocks - M, CL1 and CL2 from a 50MHz clock, of frequencies 81.3 Hz, 6.5 KHz and 1.5625 MHz respectively. I have come up with the following VHDL code, but when I create a test bench waveform it shows that the code is not working, and all three remain at logic '0' after the initial reset, before which they appear to be uninitialised. Is my code incorrect (see below) or am I making a mistake creating my test bench waveform?
    Guidance is very much appreciated.

    Code ( (Unknown Language)):
    1. library IEEE;
    2. use IEEE.std_logic_1164.all;
    3. use IEEE.std_logic_unsigned.all ;
    4.  
    5. entity signal_generator is port (
    6.     system_clk      : in std_logic ;            -- 50 Mhz
    7.     rst         : in std_logic;             -- pushbutton rst (?)
    8.     m, cl1, cl2     : out std_logic);   -- signals to be generated
    9.     end signal_generator;
    10.  
    11. architecture behaviour of signal_generator is
    12.  
    13. signal cl2_count    : std_logic_vector(5 downto 0) ;     
    14. signal cl1_count    : std_logic_vector(7 downto 0) ;     
    15. signal m_count      : std_logic_vector(7 downto 0) ;     
    16. signal cl2_en       : std_logic ;              
    17. signal cl1_en       : std_logic ;                
    18. signal m_en         : std_logic ;  
    19. begin
    20.  
    21. -- generates a 1.5625 Mhz signal from a 50 Mhz signal
    22. process (system_clk, rst,cl2_en)
    23. begin
    24. if rising_edge(system_clk) then
    25.     if rst = '1' then       -- pushbutton
    26.         cl2_count <= (others => '0') ;
    27.         cl2_en <= '0' ;
    28.         else cl2_count <= cl2_count + 1 ;
    29.         if cl2_count = "11111" then -- count upto 32
    30.             cl2_en <= '1' ;
    31.             cl2_count <= (others => '0') ;
    32.         else
    33.             cl2_en <= '0' ;
    34.         end if ;
    35.     end if ;
    36. cl2 <= cl2_en;
    37. end if;
    38. end process ;
    39. -- generates a 6.510 kHz signal from a 1.5625 Mhz signal
    40. process (system_clk, rst, cl1_en)
    41. begin
    42. if system_clk'event and system_clk = '1' then
    43.     if rst = '1' then
    44.     cl1_count <= (others => '0') ;
    45.     cl1_en <= '0' ;
    46.             else
    47.             cl1_count <= cl1_count + 1 ;
    48.             if cl1_count = "11110000" then -- count up till 240
    49.                 cl1_en <= '1' ;
    50.                 cl1_count <= (others => '0') ;
    51.                 else
    52.                     cl1_en <= '0' ;
    53.                 end if;
    54.         end if ;
    55. cl1 <= cl1_en;
    56. end if;
    57. end process ;
    58.  
    59. --generates a 81.38 Hz signal from a 6.510 kHz signal
    60. process (system_clk, rst, m_en)
    61. begin
    62. if system_clk'event and system_clk = '1' then
    63.     if rst = '1' then
    64.     m_count <= (others => '0') ;
    65.     m_en <= '0' ;
    66.     m<= m_en;
    67.         else
    68.         m_count <= m_count + 1 ;
    69.             if m_count = "1010000" then
    70.             m_en <= '1' ;
    71.             m_count <= (others => '0') ;
    72.             else
    73.             m_en <= '0' ;
    74.             end if ;
    75.     end if;
    76. m <= m_en ;
    77. end if ;
    78. end process ;
    79. end behaviour ;
     
  2. medo45mtc

    New Member

    Dec 22, 2009
    2
    0
    hi, your code seems to be more complix for a divider here is a simple pcode that i have done for you to divide 50 mhz by 31 and you can make simple change to divide as you like


    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.std_logic_unsigned.all ;

    entity signal_generator is port (
    clk,reset : in std_logic;
    clk_out: out std_logic_vector);
    end signal_generator;

    architecture behaviour of signal_generator is

    signal count_prsnt,count_nxt : std_logic_vector(4 downto 0) ;

    begin
    process(clk,reset)
    begin
    if reset='1' then
    count_prsnt<="00000" --initialize the counter
    elsif rising_edge(clk) then
    count_prsnt<=count_nxt; --fliflop for good timming
    end if;
    end process;
    count_nxt<=count_prsnt+"00001"; --the counter nxt value
    clk_out<='1' when count_prsnt="11111" else '0';
    end behaviour ;

    --this is a frq divider where clk_out is one only when count_prsnt=31
    and the frq division can be changed by changing the value of the counter
     
  3. Duane P Wetick

    Active Member

    Apr 23, 2009
    408
    19
    I find it curious that over 3000 people have looked at this post already. This problem must be used for every EE curriculum in the US and probably the world.

    Cheers, DPW [ Everyone's knowledge is in-complete...Albert Einstein.]
     
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