clock divider in VHDL - why is my code not working?

Thread Starter

keemnal

Joined Nov 12, 2007
2
Hi,

I have to generate 3 clocks - M, CL1 and CL2 from a 50MHz clock, of frequencies 81.3 Hz, 6.5 KHz and 1.5625 MHz respectively. I have come up with the following VHDL code, but when I create a test bench waveform it shows that the code is not working, and all three remain at logic '0' after the initial reset, before which they appear to be uninitialised. Is my code incorrect (see below) or am I making a mistake creating my test bench waveform?
Guidance is very much appreciated.

Rich (BB code):
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;

entity signal_generator is port (
	system_clk		: in std_logic ; 			-- 50 Mhz 
	rst			: in std_logic;				-- pushbutton rst (?)
	m, cl1, cl2		: out std_logic);	-- signals to be generated
	end signal_generator;

architecture behaviour of signal_generator is

signal cl2_count	: std_logic_vector(5 downto 0) ;	 
signal cl1_count	: std_logic_vector(7 downto 0) ;	 
signal m_count		: std_logic_vector(7 downto 0) ;	 
signal cl2_en		: std_logic ;				
signal cl1_en		: std_logic ;				 
signal m_en			: std_logic ;	
begin

-- generates a 1.5625 Mhz signal from a 50 Mhz signal
process (system_clk, rst,cl2_en)
begin
if rising_edge(system_clk) then
	if rst = '1' then 		-- pushbutton
		cl2_count <= (others => '0') ;
		cl2_en <= '0' ;
		else cl2_count <= cl2_count + 1 ;
		if cl2_count = "11111" then -- count upto 32
			cl2_en <= '1' ;
			cl2_count <= (others => '0') ;
		else
			cl2_en <= '0' ;
		end if ;
	end if ;
cl2 <= cl2_en;
end if;	
end process ;
-- generates a 6.510 kHz signal from a 1.5625 Mhz signal
process (system_clk, rst, cl1_en)
begin
if system_clk'event and system_clk = '1' then
	if rst = '1' then
	cl1_count <= (others => '0') ;
	cl1_en <= '0' ;
			else
			cl1_count <= cl1_count + 1 ;
			if cl1_count = "11110000" then -- count up till 240
				cl1_en <= '1' ;
				cl1_count <= (others => '0') ;
				else
					cl1_en <= '0' ;
				end if;
		end if ;
cl1 <= cl1_en;
end if;
end process ;

--generates a 81.38 Hz signal from a 6.510 kHz signal
process (system_clk, rst, m_en)
begin
if system_clk'event and system_clk = '1' then
	if rst = '1' then
	m_count <= (others => '0') ;
	m_en <= '0' ;
	m<= m_en;
		else
		m_count <= m_count + 1 ;
			if m_count = "1010000" then	
			m_en <= '1' ;
			m_count <= (others => '0') ;
			else 
			m_en <= '0' ;
			end if ;
	end if;
m <= m_en ;	
end if ;
end process ;
end behaviour ;
 

medo45mtc

Joined Dec 22, 2009
2
hi, your code seems to be more complix for a divider here is a simple pcode that i have done for you to divide 50 mhz by 31 and you can make simple change to divide as you like


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;

entity signal_generator is port (
clk,reset : in std_logic;
clk_out: out std_logic_vector);
end signal_generator;

architecture behaviour of signal_generator is

signal count_prsnt,count_nxt : std_logic_vector(4 downto 0) ;

begin
process(clk,reset)
begin
if reset='1' then
count_prsnt<="00000" --initialize the counter
elsif rising_edge(clk) then
count_prsnt<=count_nxt; --fliflop for good timming
end if;
end process;
count_nxt<=count_prsnt+"00001"; --the counter nxt value
clk_out<='1' when count_prsnt="11111" else '0';
end behaviour ;

--this is a frq divider where clk_out is one only when count_prsnt=31
and the frq division can be changed by changing the value of the counter
 
I find it curious that over 3000 people have looked at this post already. This problem must be used for every EE curriculum in the US and probably the world.

Cheers, DPW [ Everyone's knowledge is in-complete...Albert Einstein.]
 
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