ok, here simple edge triggered D flip flop. the AND gate reacts on specific conditions but right here i have a simple switch connected to it as an experiment.
to say it briefly; im trying to zero out Q output, whenever i turn on the AND gate. untill AND gate is closed nothing must happen, CLR will get High, and it wont react (since it reacts on Low only). system will listen to input and clock.
...so, whenever Q will be High and the AND gate's right pin also will be at High; the AND gate will release 1 from it's nose output, then inverter inverts it to 0, and this zero activates CLR. CLR takes controll over "input" and "clock" and zeroes out Q, in the very next milisecond AND gate closes since it's Q pin is zero. so CLR will get High and turn down. this must give back controll to input and clock. and so on. in short i want to zero out Q whenever AND gate switch and Q are both High .

problem is when CLR gets it's 0 and activates, it works but miliseconds later when it gets 1... it doesnt diactivates. it keeps beign in activated state forever. see picture... CLR is 1. so it should be turned down. but it's turned on ((( so it doesnt let input and clock to take controll (( does simulator lies or i didnt get something.... ????

P.S. tried on Proteus and Livewire (as i know both partially use LT Spice engine) , and i get same results... Livewire starts to toggle infinitely in the last stage. showed to 2 engineers both confirmed that my logic would work in real life... except if we missed something.... ????

 

Your circuit is very confusing. It looks like the switches have inputs connected to a ground and an earth ground. Is the ground actually +5V?

You should realize that if U1-A ever gives a "1" output, the "R" input will go low VERY fast - in nanoSeconds. It's just the propagation delay from Q to R.

This assumes your "D" input is high.

 

my switches have two states first state connects to +5V second state connects to ground, right now all the switches are connected to +5V (not ground).

my "D" input has no connection with invertert's output line. if you noticed there is no dotted connection between inverter's output and SW3. they are totally seperated. SW3 line just goes over (on top ) inverter's output line.

nothing assumes my D input; it has it's own supply source.

question still remains, why is CLR (R) input at High and still operating. it must be turned off but it isn't.

 

i couldn't find edit option so i added this new picture. since previous one confused people here is the same picture with more simplified looking diagram.

 

If you want the output to toggle on the rising clock edges with the AND gate disabled you would have to tie the not[Q] output [pin 6] back to the D input.

 

It works for me in LTspice. I used 74HC models, because I don't have 7400 series models. See attached. Download the .asc file and run it.

 

It also worked for me using another simulator [Simetrix]. I included a delay in the reset feedback purely to show up how the circuit behaves as expected.

 

ahhhh.... how i could not understand it!!! of course i could not see anything! at the moment when Q becomes 1, after nanoseconds it will be reseted. so visual graphic interface will not show this to me even if it will, my eye won't catch it. i have checked it with virtual osciliscope graph and it really gives me the results Ron H showed me. Livewire still jams. but Proteus does show that actually Q went High many times but each time it became high, in few nanoseconds it was reseted back. well.. everything works fine.when i was reading this thread my co worker (im a student here) was telling me exactly this, eye will not catch it i need a graph analysis. thank you for helping me. i hope this thread will help many others too. thank you for getting me back on the right path.im gonna help others too on this forum. bye ))

P.S. Q keeps it's High state during 30 000 Nanoseconds