Folks,
I have implemented a class D amplifier using 555 timers, couple inverters, mosfet driver and a half bridge Mosfet. The original input is 2.7V pk-2-pk.
From simulation:the amplified modulated digital signal is from 0- 8.6V Pk and amplified filtered or demodulated signal is 0.24V pk-2-pk as shown on the diagram. I was expecting a much bigger output signal - see the attachment for more info..
Why is the filtered output of my class D amplifier (attached) less than the amplified input signal?
Thanks for your help in advance.
Kkein.
I have implemented a class D amplifier using 555 timers, couple inverters, mosfet driver and a half bridge Mosfet. The original input is 2.7V pk-2-pk.
From simulation:the amplified modulated digital signal is from 0- 8.6V Pk and amplified filtered or demodulated signal is 0.24V pk-2-pk as shown on the diagram. I was expecting a much bigger output signal - see the attachment for more info..
Why is the filtered output of my class D amplifier (attached) less than the amplified input signal?
Thanks for your help in advance.
Kkein.
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