class d amp mosfet heating

Discussion in 'The Projects Forum' started by franticAAC, Mar 25, 2015.

  1. franticAAC

    Thread Starter New Member

    Jun 25, 2012
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    Hi,
    i'm designing and realizing on prototypal board the class d amplifier in figure below

    hbridge100w.jpg

    the problem is that the Infineon MOSFETS become too hot beyond the calculations that I made, also without load and with lower voltage than i need. Also they present 100ns of miller plateau at which the measured current on high side mosfet drain is of any amperes.

    I test many mosfets and they all have the same problem maybe less pronounced.

    The only one that doesn't have that kind of dissipation issue is International Rectifier mosfet in figure.

    What do you think? Is it a bad driving or parasitic components of other mosfets?

    I'm looking for a mosfet with lower Rds in order to increase output power...
    Could you help me?
    Thanks
     
  2. MikeML

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  3. franticAAC

    Thread Starter New Member

    Jun 25, 2012
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    The switching rate is 50KHz.
     
  4. MikeML

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    What sort of heatsinking for the FETs do you have?
     
  5. franticAAC

    Thread Starter New Member

    Jun 25, 2012
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    A D2pack heatsink Rth=15°C/W but now i'm doing test without it mounted
     
  6. crutschow

    Expert

    Mar 14, 2008
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    How much deadtime do you have between the switching of the upper MOSFET and the lower MOSFET?
     
  7. franticAAC

    Thread Starter New Member

    Jun 25, 2012
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    i tried different dead times from 20ns to 100ns but nothing changes
     
  8. crutschow

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    Mar 14, 2008
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    How do you generate the dead (non-overlap) time?
     
  9. franticAAC

    Thread Starter New Member

    Jun 25, 2012
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    pwm signals are generated by fpga and are connect to adum input pins
     
  10. crutschow

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    Mar 14, 2008
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    I'm trying to determine what the two signals look like that are driving the top and bottom MOSFETs in the bridge.
    Where does the deadtime occur?
     
  11. franticAAC

    Thread Starter New Member

    Jun 25, 2012
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    Could you explain me better?
     
  12. crutschow

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    Mar 14, 2008
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    Okay. I'm trying to determine if the deadtime delays are being done correctly, i.e. does the top transistor always turn OFF before the bottom transistor turns ON, and does the bottom transistor always turn OFF before the top transistor turns ON.
     
    Last edited: Mar 27, 2015
  13. MikeML

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    Especially considering the FET turn off delay as shown in the sim I linked to...
     
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