# Class A Transistor Amplifier Analysis

Discussion in 'Homework Help' started by naspek, Dec 10, 2011.

1. ### naspek Thread Starter Member

Feb 17, 2010
45
0
Hey there.. I've got couple of questions need to be answer.. i really got no idea to solve it..

1) During DC biasing measurement, if CE changes from 0.1 µF to 1 µF, what happen to the readings in VE (assume CE is ideal capacitor, no parasitic resistance or inductance)?
2) The input and output (VB and VL) waveform should be approximately 180° out of phase during resonance. VB is leading VL or in reverse way? Why?

2. ### thatoneguy AAC Fanatic!

Feb 19, 2009
6,357
718
Do you have a schematic?

Is there an Re and Rc?

Have you run a simulation on the simple circuit?

Question is: Show us the work you've done so far, including questions prior to these related to the exact same circuit, and we'll help you. We generally do not just hand out answers without students showing a good effort/thought process that is demonstrable. However, after that, assistance is free, as you'll find out.

Dec 26, 2010
2,147
298
As has been said before, please post a schematic!

1. Unless the circuit is handling a large signal, so that the DC bias is perturbed, how would you expect changing a capacitor value to alter the bias point?
2. Apparently this is a tuned amplifier, as resonance is mentioned. (Where is that schematic!) What phase angle is expected between current and voltage when a tuned circuit resonates? What is the difference between 180° lead and lag? This may be a trick question, depending how resonance is defined, and the exact circuit.

Jan 28, 2005
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hgmjr

5. ### naspek Thread Starter Member

Feb 17, 2010
45
0
so sorry for the late reply.. and thanks for uu guys replies..
this is the schematic..

6. ### crutschow Expert

Mar 14, 2008
12,566
3,080
Your schematic is much too small and blurry to see anything. Please attach a larger and sharper version.

7. ### naspek Thread Starter Member

Feb 17, 2010
45
0
http://imageshack.us/f/440/16578692.jpg/

for the clear version of my schematic..
http://imageshack.us/photo/my-images/440/16578692.jpg/

i try answering the questions.. but, i don't know whether it they are correct or not..

1.) If VE is the dc voltage across RE it does not depend on any CE change. However, the sinusoidal output amplitude will change due to change in signal feedback. Better: The gain of the stage is changing.

2.) In the frequency domain a phase shift of +180 deg is identical to a shift of -180 deg. Thus, you cannot discriminate between leading and lagging. In this case, it's helpful (and correct) to know that in fact the signal is inverted (rather than shifted in phase).

please comment on my answer.. or anything else i need to add.. because this question carry 20 marks..

Dec 26, 2010
2,147
298
You might like to estimate how much difference the reactance of 100nF or larger CE makes to the gain at the resonant frequency.
It may not be all that significant, but it needs to be compared to the rather low emitter output impedance -
roughly = Rs/(β+1) + 0.026/Ie.

This will probably not be required for your problem, but there is actually a hidden danger in having CE small with a tuned collector load, when the base is fed from a low impedance. Parasitic capacitances in the transistor and wiring can sometimes convert this sort of circuit into an oscillator, particularly when the load circuit Q is very high. I had exactly this situation quite recently, with a circuit Q of about 200 working at about 100kHz.

Your circuit has only 1kΩ load, so is not so likely to suffer in this way.

Last edited: Dec 10, 2011
9. ### naspek Thread Starter Member

Feb 17, 2010
45
0
how about the second question..? why 180 degree and who's leading or lagging?