Hi AAC community,


I need help for my circuit. This questions may be stupid but try to bare with me. My question is:

I have a up/down counter and some logic gate to detect the "HIGH" signal when number 9(1001) appears. I will push the up counter button to count up till it reaches 9(1001), then push the down counter button till it reaches 0(0000). I noticed a small spike when the counter down from 8 to 7(1000). Is there a way to filter this out. I am new to electronics so if anyone can give me step-by-step advice?


Here is the picture:
http://farm7.static.flickr.com/6041/6328324154_eb7da565a4_b.jpg


Thanks

 

Welcome to AAC.

First try to put a 100nf ceramic cap across supply pins of all the logic IC's. As close as possible to the IC's

 

Hi Rifaa,

thanks for replying. The logic gate in multisim has no vcc and ground as you can see in the pic. do i connect at the outputs of the counter(Q0-Q3)?

 

I believe it's a synchronous counter, right?

 

Hi,

Got this from the data sheet. So i guess it is.
"LS192 and LS193 are Asynchronously Presettable Decade and 4-Bit Binary Synchronous UP/DOWN (Reversable) Counters."

thanks

 

You have to use Asyn counter to avoid that glitch Mate

 

the problem is i can't change the 193 ic so they expect me to fix the glitch myself. :[

 

I thought you had made the circuit.

It's a home work right ?

 

You have to use Asyn counter to avoid that glitch Mate

Are you sure. I think it should be opesite. Synchronous operation is having all flip-flops clocked simultaneously. So that the outputs

change together when so instructed by the steering logic. With asynchronous (rippleclock) counters. You will have output counting
spikes normally.​

 

The problem you are observing is caused by "race". The way to avoid this is to draw a Karnaugh map. Then you will find that the simplest solution is one AND gate with QA and QD as inputs.

 

kind of. I designed the circuit but I am only give the 74LS193 and logic gates.

 

hi Mr Chips,

I tried that at the start but got the "small spike" while counting up and down, [9 to 8 spike] [8 to 7 spike appear],

Then I did the circuit above and got a "small spike" when counting down [9 to 8 - no spike] [8 to 7 spike appear].

I use the oscilloscope to check and gates U1A and U2B. The spike source was from and gate U1A. So I was wondering if there is a way to filter out the slight delay.

Thanks

 

Is this a real circuit or a simulator?
On another note, there is another thread going similar to this. You must debounce your clock push buttons.

 

I plan to test on simulator then move to actual circuit. similar thread. I cant find the thread. May I know the title so I can relate the solution to my question. Did you mean the up and down push button.

Thanks

 

You could try this. Swap around the signals. So both the inverted inputs end up on the same gate. Then replace this gate and the inverters on the input with a NOR gate.

 

I just tested the real circuitry it out and it works. Strange? Should not trust simulators... haha. Thanks guys any way.