circuit protection schematic design (OrCAD)

Thread Starter

Skyland

Joined Jul 1, 2014
28
I have designed a protection circuit for my pcb and I would appreciate having some feedback before starting the PCB design.

The circuit is broken down as follow;

-ESD protection provided by a one channel IC

-low pass filter to suppress noise above 4.5Khz

-pmos to protect against reverse polarity

-crowbar for overvoltage protection

-current sensor which is connected to a uC ( ideally I would like the op amp to work with the PSU IN in the range 3.3v to 16v)

The maximum voltage is 16V and the minimum votlage is 3.3V.
 

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If you have the possibility you should either replace the output Opamp to a rail-to-rail opamp or increase the power supply voltage to the Opamp, because with a OP471 and a single 5V supply you have very little useful range to work with.

Having said that it depends on the current, sense resistor and the gain you want...etc
 
Also if you are going to operating at 3.3V to 16V, you might want to consider a logic level FET...not sure the one you have is a logic level FET, going by the drop across the FET.
 

RichardO

Joined May 4, 2013
2,270
Although Q2 protects most of the circuit from reverse voltages, it does not prevent negative voltages on C3 and C5. Remember to make sure that C3 and C5 are non-polarized caps such as X5R or X7R ceramic.
 

Thread Starter

Skyland

Joined Jul 1, 2014
28
The current monitored is in the range of 0 - 1A . ADC is from 0 - 3.3V

The actual models used have been implemented in the schematic for clarity.

The supply voltage range is from 3.3V to 16V

The low pass filter has been replaced by a ferrite bead

Differential Op amp is used for current monitoring with 165K for R load to provide the adequate gain (0 to 3.3V input to the ADC).
 

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RichardO

Joined May 4, 2013
2,270
When you replaced the inductor and caps with the bead you removed all power supply bypassing. You need to add a 0.1 uF ceramic cap from the Vin+ pin of U1 to ground. I would also add a larger capacitor such as a 4.7 uf in parallel with the 0.1 uF to help remove large power supply transients.
 
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