i would like to know whether this circuit will be able to work ?
the circuit is design such that the output Q will be low from 0000 - 0110 and high when 0111 - 1111. then the cycle repeat.
when the PRE and CLR is 1, it will look for input of JK. when JK is 00, the output Q will remain no change. however when J is 1 and K is 0, will the output Q be 1?
is it true that when either PRE or CLR is not 1, the output Q will not be dependent on JK input?
the circuit is design such that the output Q will be low from 0000 - 0110 and high when 0111 - 1111. then the cycle repeat.
when the PRE and CLR is 1, it will look for input of JK. when JK is 00, the output Q will remain no change. however when J is 1 and K is 0, will the output Q be 1?
is it true that when either PRE or CLR is not 1, the output Q will not be dependent on JK input?
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