Discussion in 'Homework Help' started by aaf8888, Dec 29, 2011.
Can any body please help me with this question here...The question is attached>>>
Can you be more specific about the problems you are having and post some of your work?
The basic topology of the circuit as indicated in your title is a common emitter stage to establish your gain followed up by a emitter follower stage which should allow you easily establish the desired output resistance.
You have a basic H biasing scheme on the common emitter stage so start by selecting the appropriate bias point and selecting component values to achieve the desired bias.
If you have anymore questions, just ask.
I want to know how to start solving this problem...any suggestions
You will need to make a couple of initial assumptions and perhaps go through a couple of iterations to 'tweak' the design.
A gain of 35dB is equivalent to a voltage gain of ~56. Given the common collector stage will have a gain slightly less than unity, I would suggest setting the gain of the CE stage at ~60 (say).
The CC stage should have high enough input resistance that its input resistance can be ignored for the initial gain adjustment of the CE stage.
The CE stage gain would be approximately determined by
where I use
One would normally set the CE collector bias voltage at around Vcc/2=4.5V
Next choice would be a suitable collector current - why not start with say something in the 1-2mA range and see where that gets you.
Given Ic1 & Vc1 you can then decide on a value for RC1 which, for a given Av then leads you on to a value of RE1A - with re known from the above. Subsequently one then decides on a suitable value for VE1 to lead into a value of RE1B. From there you decide on the base biasing arrangements for Q1 and then onto values for R1 & R2 - which in turn play a role in determining the total Rin value.
Thank you very much that really helped very much...
One last question...What about the cc stage How do I find R3 and RE2...
Use the condition for your output resistance as you look from the emitter to the base of the CC stage.
Also, for the biggest signal swing at the output, you'd want your emitter to sit at half the power supply voltage. If you want to achieve this at the emitter select the bias point at the base to sit at half the supply voltage PLUS the drop across the base emitter junction. (i.e. Half the supply + 0.7V)
Note that for the largest swing you'd want to select your collector resistance to be as small as possible.
You decide what current flows through the transistor, and from there ohms law will deduce the value of the resistance in the emitter. From here you can select the collector resistor based on the output resistance condition.
Hello, thanks everyone for the help!
I want to ask T N K if he's available, what did you mean by choosing collector bias at 4.5V ? I'm stuck at choosing the right R1 - R2 .
I need urgent advice. Thanks in advance.
The suggestion was that the various parameters such as collector current & voltage would be chosen as practical values. Hence setting the collector voltage to ~4.5V seemed reasonable.
Write a voltage divider equation using R1 and R2 and equate it to 4.5V.
From here select the appropriate values for R1 and R2.