I have a project to make single stage CE amplifier but I have been given very limited information so I don't know how to calculate the values of components.
The only given values are:
Voltage Gain= 70
Lower cutoff frequency= 70 Hz
Load Resistance= 7k ohm
Vce= 7v
Ic= 3mA

Please note that am not looking for someone to solve for me this project I just need your advice on where to start & recommend me where to get the steps for calculating the values for rest of Resistors & Capacitors. I have googled alot but I can't get an example with similar given values.

The circuit is similar to bellow with Transistor 2N2222

 

Experts your help is highly appreciated . . .

 

Load Resistance= 7k ohm

For maximum power transfer, output impedance matches load resistance. Make R3 = 7-kohm. R4 is for thermal stability, and can be small. Make it 20 to 50-ohm, making (with Re = 20-ohm) Ve = 60.8mV

Ic= 3mA

Ie = Ib+Ic, and Ib is about Ie/Beta. This gives Ie = Ic/(1-1/Beta). You'll have to look it up or measure it, but using Beta=75 gives Ie = 3.04-mA and Ib = 40.5-uA. Biasing branch current must be much larger than injected current to remain steady, so Ibias ~ 10*Ib = 0.4-mA. You'll have to look up the ideal Vbe for maximum gain, but choosing 0.7V is a pretty good guess. This gives R2 = Vb/Ibias = (Ve + Vbe)/Ibias = (60.8-mV+0.7V)/0.4-mA = 1.9-kohms. I think you can deal with R1. The bypass capacitors will have to be large'ish to pass a 70 Hz signal -- maybe 10uF each.

 

appreciate your help

I already calculated Ib=Ic/beta=40uA, Ie=Ic+Ib=3.04mA, I really don't understand what you mean by Ibias! Can you give me the calculation steps for R1, R2,R3,R4 C1, C2 & CE
Sorry for asking too much but I need to learn & report what I learned as well.

 

Ibias is the current that goes through R1 and R2, the "bias leg". Do you know what C3 does?

 

The basic equations are:

VC = (Vcc / 2)
R3 = [(Vcc - VC) / IC]
R4 = (VE / IC)
VB = (VE + Vbe)
ID = (10 x Ib)
R2 = (VB / ID)
R1 = [(Vcc - VB) / ID]

 

Ibias is the current that goes through R1 and R2, the "bias leg". Do you know what C3 does?

No I know nothing in this circuit after reading many different tutorials am still confused

 

The basic equations are:

VC = (Vcc / 2)
R3 = [(Vcc - VC) / IC]
R4 = (VE / IC)
VB = (VE + Vbe)
ID = (10 x Ib)
R2 = (VB / ID)
R1 = [(Vcc - VB) / ID]

Can you tell me what is ID!

 

Here is a working EXAMPLE.

With VCE @ 7v.
I'll choose 1v. to be dropped across R4.

That makes 1v / 3mA. ~= 330 ohms.

Now 7v. + 1v. = 8v. to be read at the collector from ground.

That would make Vcc = 16v.

Now 8v. will remain across R3, and 8v / 3mA ~= 2.7K ohms, for R3.

That is a rough DC gain of around 8.

Now 1v + Vbe of 0.7v. = 1.7V. This is the voltage at the base (VB).

By making R2 to be around 10 times R4 will take care of any base current loading on the voltage divider.

So I'll choose R2 to be around 10 times R4, which is around 3.3K ohms.

Now ID = VB / R2 which is 515uA

Now R1 is calculated as [(Vcc - VB) / ID] = [(16 - 1.7) / 515uA] = ~27K ohms.

Thats an example of calculating resistor bias values.

 

If you don't know what C3 does, then don't use it. You will want to read up on "coupling capacitors" and "thermal stability".
http://en.wikipedia.org/wiki/Bipolar_transistor_biasing#Collector-Stabilized_Biasing

 

Here is a more thoro explanation.

Every design is unique depending on the criteria that is given.
The values given must be looked over to determine how your design will be worked about.

Your values given, have 2 facets, to it,

1). the preset values (constraints)
2). values to work towards (value goals)

The constraints are:
1). VCE = 7v. That is a given and the design must adhere to that.
2). IC = 3mA. again must adhere to it.
3). load resistance = 7K ohms given and does not change.

The goals are:
1). Voltage gain
2). cutoff frequency
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Start the design looking at the constraint values first.

VCE = 7v
IC = 3mA.

Arbitrarily choose a value for VE (emitter voltage), this is the voltage across R4.
So I chose 1v. for that value.

By adding the (VE + VCE), that would give a new voltage (VC), which is the voltage that will be at the collector with respect to ground reference. (this is also known as the output voltage, because it is referenced to ground, where all the signal voltages are referenced from) However this is not the signal output voltage, but the DC bias voltage.

Now with VC established as 8v. due to (VE + VCE), then the supply voltage needs to be double that value to aquire proper output swing of the signal voltage.
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Note here: if the signal voltage output was given as a value, then the supply voltage would be calculated in a different way.
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However all calculatiuons for this design, is only working with the values you were given.
This design procedure is only good for these particular constraints given.
If other constraints were given then the design procedures would be implemented in different ways.
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So now that would make VCC (supply voltage) = 16v.
Now that VCC has been calculated, the values for the bias resistors can be worked out.

Start with R3.
R3 = [(VCC - VC) / IC] = [(16v. - 8v.) / 3mA.] = 2666 so make it a nominal value. say 2.7K ohms.

R4 = (VE / IC) = (1v. / 3mA) = 333 make it 330 ohms.(nominal value).
Assuming a value of 0.7v. for Vbe, then the voltage at the base would be (VE + Vbe) = (1v. + 0.7v) = 1.7v. for (VB)

Now for this application only because input impedance is not a constraint, you can choose a value suitable for the values worked out.

So make R2 = (10 x R4) = 3.3K ohms.

Now ID is the current in this voltage divider consisting of R1 and R2.
Therefor ID = (VB / R2) = (1.7v. / 3.3K) = 515uA.

R1 now calculates out to [(VCC - VB) / ID] = [(16v. - 1.7v.) / 515uA.] = around 27K ohms.

So now you buiuld the circuit and check to see if you have close to (VCC / 2) at the collector of the transistor, referenced to ground, then check the voltage at the emitter and base to verify the bias voltages are CLOSE to the calculated values.

If they are then you have the transistor stage conducting in its linear (amplifying) region.
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Your voltage gain will then have to be aquired through C3, which is another lesson in itself.


This is just to show you how to start to get the bias voltages when working with the constraints.
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It is up to you to rework the values as well as calculate C3 to get the value goals.
You may have to choose another value for VE to obtain a better goal design.
To meet the gain requirements...

That's where a thoro understanding of impedances and reactances of capacitors comes into play.
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Again this design procedure for biasing the transistor into its linear region for amplification, has only been implemented by the constraints you were given.
If any constraint were eliminated or changed or others added, then this design procedure would need to be changed accordingly.

 

So now you buiuld the circuit and check to see if you have close to (VCC / 2) at the collector of the transistor, referenced to ground, then check the voltage at the emitter and base to verify the bias voltages are CLOSE to the calculated values.

first big thanks for the valuable info. Ok I worked out the calculation as you told me & build the circuit on but when I connected the DC Voltmeter across R3 or RE .. It is not giving any value! I attached snapshot of simulation

 

I'm not sure how that simulation program works, but it looks like the battery is not hooked up properly.

Battery needs to be 16v.

The negative side needs to be connected to ground terminal.

Break the connection between B1 and C1. and connect that B1 side to ground terminal.

And take all the readings using the ground terminal as the reference.

Also C3 is where you will obtain the gain requirements.

Here is an equation to solve for C3 value.
again this is only a method for the parameters you were given, if other parameters were given then other methods would need to be applied.

Ro = (RL x RC) / (RL + RC)

Av = voltage gain. given as 70.

Xc = Ro / Av

C3 = [ 1 / (2 x pi x freq. x Xc) ]

then choose a value larger than calculated value.

 

OK I met the instructor today & he gave me some useful tips in another way which has some difference so I was able to made new calculations:

Vce=8 is given & Vce=Vcc/2 so Vcc=16v
VE is 10% of Vcc so VE=Vcc/10=1.4v
Vb=Ve+Vbe=8.4v
beta=75=Ic/Ib so Ib=40 mico
Ie=Ic+Ib=3.04mA
Rc=Vc/Ic=2.8k we make it a bit less to 2.7K
Re=Ve/Ie=460.5 so we take the 470 ohm
IR1 is current across R1 which is = 10xIb=400 microA
IR2 is current across R2 = IR1-Ib=360 microA
VR2=Vb
VR1=Vcc-VR2=11.9v
So now since we have got both current & voltage across R1 & R2 Ohm's law is our leader which results in:
R1=29.75K am not sure what is closer available resistor for this value!
R2=5.8k maybe this one is close to 4.7k!!??

In regards to Capacitors I found some similar formula C3 or CE=1/(2 x pie x fc x Xc)
fc is my cutoff frequency=70 Hz >> given
but now getting Xc in the method I have is different:
Av x 0.707=RL'/re' x Xce (0.707 is constant value)
re'=25/Ic
RL'=Av x re'
After applying my values on above formula CE=0.658 microF
C1==1/(2 x pie x fc x Rin)
where Rin=1/R1+1/R2+(beta x re')
This gives C1=3.63 nanoF
The formula for C2=1/(2 x pie x fc x RL') which gives C2=3.89 nanoF

Thats the way I used to get capacitors but is this sounds right??? as I am getting answers in "Nano"

Now:
Using the above method results as the Xc=3452
Using the formulas you provide results as Xc=2.8.57

Very big difference in there which is going to effect the value of CE!! Plz advice me in this

Also how will I get C1 & C2 as per the method you have?
U

 

Hi,

First of all, do you see how close the bias resistors are in value, even using 2 different methods.

RC @ 2.7K RC @ 2.7K
RE @ 330 RE @ 470
R1 @ 27K R1 @ 29K
R2 @ 3.3K R2 @ 6K

The method I used I didn't take Beta into consideration, but chose to make R2 ten times larger, to make up for any beta changes.

That should show that different design techniques can be implemented for the same design parameters. There is no one method that does it all, each design can have several solutions.

That being said, the method you were given, is the more professional approach, and it is very good to learn that approach as well as possible, until you understand the reasons for using the methods given.

The question about the capacitors.

Follow everything your instructor gave you on the coupling / bypass capacitors.

The method I used was a first order assumption, to get into the ballpark range.

I simply took the total output impedance, of RC in parllel with the load, and got the new impedance value.

Then divided that impedance value by the voltage gain of 70, to get the value of the capacitive reactance (XC).
In short I'm using the XC value to substitute the RE in the formula for voltage gain. (Av).

Av = Ro / RE so now Av = Ro / Xc

the DC gain is (Ro / RE) and the signal gain is (Ro / XC.)

As I said this is just a first approximation approach, for the constraints given.
If impedance in (Zin) was given, than CE would need to be calculated in a whole different way, to meet the impedances required.

From what you have shown in your post above, it seems you are getting a good sense of understanding of how to design this kind of circuit.

Keep up the good work, and if there are more questions, please keep asking, because a lot of experianced knowledgeable people on this board, are more than happy to help you.

 

in regards to the Capacitance calculation it was not given by instructor I just picked up that method from some colleague.

I have made the circuit on ORCAD pspice & put my calculated values on the components but when I did simulation I did not see any amplification occurs on the signal.

I have attached a snapshots. Can some one please advice . . .

 

Because it is impassible to current to flow through so small capacitor if input signal has 50Hz.
For F=50Hz C_in > 3.6uF and C_out > 470nF; Ce > = 360uF

 

As joni130 said, the capacitors are reacting and submitting a impedance to the signal.

Using this equation, to solve for capacitive reactance.
Xc = [1 / (2 x pi) x freq. x C]

XC1 = [1 / (6.28 x 50 x 3.63nF)] =~ 877K ohms.
XC2 = [1 / (6.28 x 50 x 3.89nF)] =~ 818K ohms.
XCE =~ 4.8K ohms.

Here is a rule of thumb,
XCE (capacitive reactance), should be around 1/10th of RE at the frequency of operation.
So to calculate XCE you would first determine the 1/10th value of RE which in this case is (460 / 10) = 46 ohms. This value will now be the Xc in this equation.

CE = [1 / (6.28 x freq. x Xc)] = [1 / (6.28 x 50 x 46)] =~69 uF. Choose a value higher than this to ensure all frequencies are passed.

Now back to your circuit.

after you change the values of your capacitors, than you need to change the input voltage as well.

The input voltage should not go above 1v., this is a small signal amplifier, so anything above 1v. begins to over work the transistor, to cause it to produce distortion on the output signal, as well as distortion of the signal going in, too.

Once this is done, simulate it with a 10mV signal input and see if there is any distortion on the negative peeks, than increase the input voltage until you get heavy clipping on the neg. peeks.

Also it is a good rule to try to bias the transistor collector so it has as close as possible 1/2 the supply voltage dropped across RC.

Taking a look at your circuit, lets to a first approximation analysis, assuming the base current has NO affect on the voltage divider, lets determine the currents and voltages in key areas.

Voltage at the base (VB) would be [VCC x R2 / (R1 + R2)] =~2.28v.
Voltage at the emitter (VE), would be approx. 0.5 to 0.8 v. lower, so use 0.7v. for first aprox. which makes VE =~1.58v.
Now the current (IE), flow through RE is (VE / RE) =~3.43mA.
For first aproximation, assume this current (IE) to also flow through RC, and the voltage drop across RC = (IE x RC) =~9.63v.
So now to determine the voltage at the collector, take supply voltage (VCC), minus the voltage drop across RC, and the remainder is the voltage that is measured at the collector terminal from ground, called (VC).

So VC = (VCC - VRC) =~4.36v.

Now this will work but very sensitive to input signals, before it goes into distortion on the output signal.

So lets look at your output signal when the input signal is applied.

First the input signal goes from 0v. and drops below 0v. as the signal goes negative, the transistor collector voltage goes positive in sync, with the drop in input voltage, and completes a positive sinewave peek, then as the input signal goes back to 0v. and begins to rise above 0v. again the transistor collector voltage will begin to drop in voltage in sync. with the input voltage rise, However, because your collector voltage is already at a lower value than 1/2 of VCC, then the output voltage can only drop so far before it can't drop any lower it has hit bottom, and as the input signal continues to rise the output signal keeps a flat output voltage, because it has bottomed out, this is called clipping of the negative peeks, you have the complete positive peeks, but your negative peeks are clipped off, and so this distortion will show up on an osciloscope, and if in audio range, will be noticeable, to the listener.

HOWEVER:
I think you put the wrong VCC value on your simulator, if it was 16v. instead of the 14v. it would probably be closer to VCC/2, so you can have less distortion, on more input signal.
Then simulate it and see if you can get a larger input signal then before with less clipping as before.

 

hobbyist CE capacitor see form his terminal RE resistor and parallel connect resistance seen from emitter looking into the BJT ( R1||R2 / (β+1) + re )
So CE time constant is equal
T = CE * Rt
Rt = RE || ( R1||R2 / (β+1) + re ≈ re

So for 50Hz we get
Ce > 0.16/ ( 50Hz * 26mV/3mA ) = 369uF

 

HARASI,

Follow the method joni130 shows, that is a more accurate approach to your question.

I was showing a first approximation method, which is very apparent, there needs to be more factoring in, on impedances, rather than just the RE value alone.