CD74AC164P won't shift --- Pls HELP

Discussion in 'The Projects Forum' started by RLT, Aug 8, 2014.

  1. RLT

    Thread Starter New Member

    Aug 8, 2014
    11
    0
    Shift register (S/R) CD74AC164 conditions:
    Pin 1: +5V,
    Pin 2: +5V until next 100 nsec CP - (sets Q0 (pin 3) high),
    Pin 3: Stated above.
    Pins 4 thru 6 and 10 thru 13: low,
    Pin 7: Gnd,
    Pin 8: 100 ns period CP, repetitive 72 ms,
    Pin 9: Initially low, now high,
    Pin 14: +5V

    Initially, S/R was cleared (low), now high. Set the first bit (Q0) high, verified on scope. The CP that ended the Q0 bit did not transfer that bit to Q1. The period of the set bit is 72 ms.

    My question: Why didn't Q0 (pin3) transfer to Q1 (pin 4)?

    Thank you!!!
     
  2. Papabravo

    Expert

    Feb 24, 2006
    10,179
    1,800
    What does this mean:
    Pin 2: +5V until next 100 nsec CP - (sets Q0 (pin 3) high),

    How about a schematic instead of this useless pin list.
    It is possible that you have a setup time violation.
    What does your clock pulse look like? Normally high with low going pulse, or normally low with high going pulse. The rising edge is the active edge of the clock.
     
    Last edited: Aug 8, 2014
  3. RLT

    Thread Starter New Member

    Aug 8, 2014
    11
    0
    This is one component of the project containing hundreds of components. The pertinent information is supplied with the exception of one error, the CP is 100 usec not 100 nsec. A schematic alone without the pin information would be useless. I attempted to paste TI's data sheet, but to no avail.

    Timing violation may be possible but I don't see how. As I understand, the positive going CP is synchronous, clocking all FFs simultaneously. The transition should transfer a high bit to the following FF and reset (drive low) the previous bit.
    As shown below:
    Q0
    ___---__________
    positive going CP should result in:
    Q1
    ______---_______
    I'm getting:
    Q0 Q1
    ___---__________

    The top two Q0 and Q1 notations should be located above the high state. The text editor forced them to the left margin.

    The clock pulse required is edge triggered, normally low going high.

    With the IC removed, I measured the resistance between the IC's output (Q1) and ground...>18 Mohms.

    I've tried several ICs, all the same response. I can't believe I have 14 defective chips. I must be doing something wrong!
     
    Last edited: Aug 8, 2014
  4. crutschow

    Expert

    Mar 14, 2008
    13,056
    3,245
    Well, we really need a schematic of the hookup to the IC (don't need the IC internal circuit) to determine what might be wrong. A careful hand-drawn one is acceptable if you can't do it on a computer. (So how did you build the circuit if you don't have a schematic?)
     
  5. RLT

    Thread Starter New Member

    Aug 8, 2014
    11
    0
    I have never uploaded anything to a forum before. Hopefully, this works. Please excuse my ignorance.

    Two files should be included:
    A word doc containing a .jpg image of the print and TI's data sheet.

    The subject ICs are U22 and U32 near the top of the print.

    Hope this helps!
     
  6. crutschow

    Expert

    Mar 14, 2008
    13,056
    3,245
    Your drawings came through okay but the .jpg image in the .doc is too blurry to readily read (did you look at it after it was posted?). Jpegs are bad for drawings as its compression algorithm, designed for pictures, tends to blur sharp edges. Please post as a .pdf or other bit-map type file (bmp gif png, etc.).
     
  7. RLT

    Thread Starter New Member

    Aug 8, 2014
    11
    0
    Attached, find a screen-shot of U22's timing.

    Thank you!
     
  8. RLT

    Thread Starter New Member

    Aug 8, 2014
    11
    0
    Hi Crutschow,

    I was apprehensive about posting the schematic because of its size and the possibility of not being readable.

    Logic Works 5 was used to design and draw the project. I don't know if or how I can convert to another format.

    LW-5 was designed around TTL; some changes were required to convert to CMOS. However, everything works except the shift-register stepping. The initial bit generation works and can be seen in the attached timing screen-shot.
     
  9. crutschow

    Expert

    Mar 14, 2008
    13,056
    3,245
    Can you post a screen-shot of just the area in the schematic of interest?

    Note that, although I can read Word files, many cannot. Can you dump it to Paint or other graphics program and post it from there?
     
  10. RLT

    Thread Starter New Member

    Aug 8, 2014
    11
    0
    Great idea Crutschow,

    Uploaded is a word doc of a localized screen-shot with LW-5 timing.
    Also uploaded in Paint (.png) program that will yield better results for all to see.

    Thank you!
     
    Last edited: Aug 8, 2014
  11. MrCarlos

    Active Member

    Jan 2, 2010
    400
    134
    Hello RLT

    ! wow !, Really, as you mentioned, is a very large scheme.
    But unfortunately I do not understand what it does, or you want to do, that design.
    including analyzing all documents you have attached

    Let me do a little reminder of how it works 74164 IC.
    PIN’s 1 & 2 make an AND function.
    If you want to have a high level Q1, both inputs must have a high level.
    if you want to have a low level Q1, any input must be low. Or course both inputs low.

    While it's Reset input is high (False). . .
    The result of the AND function, will be acquired by Q1 in the next positive transition of a pulse applied to the input clock.
    Q2 will be acquired Q1. . .
    This way:
    Q1 -> Q2,
    Q2 -> Q3,
    Q3 -> Q4 Etc.

    Now: You say in your original post: Pin 1: +5 V,
    Therefore the state at pin 2 will be acquired by Q1, the next positive transition of the pulse applied to the clock input. This, of course, if the reset signal is false. high.
    But if the Reset signal is true, low, all Q's are erased to low level.

    To Me, I think it would be better if you attached the file that generates your LogicWorks 5.
    You can compress it with WinZip or WinRar and attach it to your next message.
     
  12. RLT

    Thread Starter New Member

    Aug 8, 2014
    11
    0
    Hi MrCarlos,

    Your assessment of the S/R operation is correct. To generate the first bit, pin 2 is high while the first CP goes high. The next CP should transfer the first bit to the second FF. This is not happening.

    I don't think the LW-5 file can be opened outside of LW-5. Also, the file can only be saved to LW-5. If I zip the file nobody can open it without LW-5.
     
  13. MrCarlos

    Active Member

    Jan 2, 2010
    400
    134
    Hello RLT

    You Say:
    Your assessment of the S/R operation is correct. To generate the first bit, pin 2 is high while the first CP goes high. The next CP should transfer the first bit to the second FF. This is not happening.

    Yes, that's exactly what we know.
    But why that happens, there may be many assumptions:
    1- Clock signal does not reach on time.
    2- The Data is erased by applying the Reset signal. . .
    3- Etc cccc.

    For that and many other reasons I prefer to have at hand the file that is generated by your simulator LW-5.

    The file that is generated with your LW-5 has the CCT extension, and clear, its name.
    Ok. You can compress with WinZip or WinRar that file and upload it here.
    As I see it, I unzip with WinZip or WinRar and then I can simulate it in my LW-5. . Easy No?

     
  14. RLT

    Thread Starter New Member

    Aug 8, 2014
    11
    0
    Hi MrCarlos,

    Everything works great in LW-5. The problem showed up after construction.

    Attached, find a screen-shot showing the timing and the transfer of data from one register to the next, etc.

    If everything is working, how can having the LW-5 schematic help?
     
  15. MrCarlos

    Active Member

    Jan 2, 2010
    400
    134
    Hello RLT

    ! oh ! I see.

    The problem is in the circuit you built physically.
    Now we have to look at this issue from another point of view.

    There are lots of things that could be causing this fault.
    Poorly filtered power source, unstable, with electromagnetic noise, Etc.

    If you did the PCB there is probably a defect on It.
    False contacts in solder. left a PIN without soldering, Tracks on the PCB making short circuit each other.
    Etc.

    If you did your circuit on a universal board, with wires, is likely to be some wire elsewhere.

    I suggest you concentrate on analyzing the connections in those ICs that present failures. very, very carefully.

     
  16. bertus

    Administrator

    Apr 5, 2008
    15,649
    2,348
    Hello,

    I have some questions written in a part from your drawing:

    [​IMG]

    And if there are back EMF diodes mounted, they can distroy the gates, as reverse polarity is possible.

    Bertus
     
  17. eetech00

    Active Member

    Jun 8, 2013
    652
    112
    Hi RLT

    I don't see any bypass capacitors anywhere on your schematic.
    If you don't use them, noise can cause spurious logic transitions.

    Did you install a bypass capacitor, usually a 0.1uF or 0.01uF cap,
    close to each IC power supply pin on the manufactured circuit?

    eT
     
  18. RLT

    Thread Starter New Member

    Aug 8, 2014
    11
    0
    LogicWorks does not support actual relays while running the simulation, so I used LEDs. The relays purchased do have spike suppression diodes.

    The relays require only 10 mils...they have 500 ohm coils, These are small-signal relays having milliamps through the contacts.

    Bypass caps are used to reduce P/S noise. Again, LW only supports TTL logic. It's not a spice program. At least not to my knowledge.

    While the project uses CMOS, the symbols were taken from LW's component list; important notations regarding TTL to CMOS changes, were noted on the print (schematic).

    Thanks for your responses!
     
    Last edited: Aug 10, 2014
  19. RLT

    Thread Starter New Member

    Aug 8, 2014
    11
    0
    Hi Bertus,

    I think you just solved the problem!!! When the 08s are high and the 164's are low, there is no current limiting to protect the 164s. My guess, the 164s became fuses, or possibly welded to ground. I'll have to set up something to test the 164s.

    I'm in my 70's and have been involved with bench work and design all my life. I can't believe I didn't see this coming. THANK YOU!!!

    The relays will pick at <3.8V, maybe I can install blocking diodes on the outputs of the 08s???
     
  20. RLT

    Thread Starter New Member

    Aug 8, 2014
    11
    0
    Checked all the 74AC164s; all were good. Installed a diode between the 74AC08 and the common of the relay coils to block current when the 74AC08s were high and the 74AC164s were low.

    The problem: The 164s were not shifting due to the rise time being too long, ~200ns. Installed a 74HC14 (Schmitt trigger); the rise time is now ~20ns and the registers shift correctly.

    What did become fuses, however, were the diodes in the relay modules. Oh well, I guess I'll have to install 110 diodes...certainly far less expensive than replacing the relays.

    Thanks to all who responded!
     
Loading...