CD4047 multivibrator : astable and astable bar inputs.

Discussion in 'General Electronics Chat' started by vks_foe, Jun 15, 2015.

  1. vks_foe

    Thread Starter Active Member

    Jan 11, 2009
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    Can somebody please clarify the use of the various combinations of astable and astable_bar inputs of CD 4047 multivibrator IC.
    Does it act as hold/pause (memory) function ?
     
  2. dl324

    Distinguished Member

    Mar 30, 2015
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    From the datasheet:
    4047function.jpg

    And to answer your question - no.
     
  3. AnalogKid

    Distinguished Member

    Aug 1, 2013
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    While the 4047 has several flipflops in it, none of them are configured as data latches (if that's what you meant by "memory"). As for the hold/pause, both the True and Complement Gating inputs allow this. BUT - as indicated in the logic diagram on page 2 of the datasheet, pausing the astable terminates the current clock cycle. If the output (pin 13) already was in the low state, it just sits there. If it was in the high state, it drops low immediately and sits there. Thus, when enabled the oscillator always starts out with a clean first cycle.

    ak
     
  4. vks_foe

    Thread Starter Active Member

    Jan 11, 2009
    55
    5
    Thanks... what i need is only the hold/pause function for Q and Q_bar (pin 10,11).. from your reply, i hope that can be done..
     
  5. dl324

    Distinguished Member

    Mar 30, 2015
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    One shots are used for generating pulses that are timed by an R/C network. The output pulse can generally be shortened by resetting the OS, and some can be retriggered; but I have never heard of one that could be paused because the timing element is a capacitor being charged/discharged.

    It might be better if you describe the functionality you desire.
     
  6. AnalogKid

    Distinguished Member

    Aug 1, 2013
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    Good point. When you pause the oscillator, the output will go to the low state and wait, but the timing capacitor won't just sit with whatever charge was on it at the time. Pin 3 goes high and pin 1 goes low, so there is almost Vdd across the timing cap. This is why the first half-cycle after the oscillator is re-enabled is longer than when it is running normally.

    If you want a circuit where the output can be paused in the middle of a cycle and it picks up right where it left off with the remainder of that cycle, you can start with a higher frequency divider and a longer divider to reduce the half-cycle ambiguity to a smaller percentage of the output period.

    ak
     
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