casecading decade counters

Discussion in 'The Projects Forum' started by WVU Engineer, Feb 9, 2008.

  1. WVU Engineer

    Thread Starter Member

    Jan 18, 2008
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    i am looking for information on how to cade decade counters/ What i basically want to happen is to have 30 led's light on one at a time... and the previous one turn off. The only problem i am having is cascading the chips so that when the 10th light of the first chip turns off, the next one lights up. Any body have any ideas? I have a bunch of he cd4017be chips. Any suggestions would be a big help, thanks
     
  2. beenthere

    Retired Moderator

    Apr 20, 2004
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    My Motorola CMOS manual shows doing that with a series of 4081 AND gates. Each has an input common with the clock. The Q9 output of each 4017 goes to the CLOCK ENABLE NOT input to disable each 4017 in succession as the count increases. That Q9 output also feeds the other input of the associated 4081, and lets the clock go to the next 4017. Q0 of each 4017 is tied to the next stage's RESET input, and the last 4017 has Q9 led back to the beginning 4017's RESET, so the counting string will begin again from 0.
     
  3. SgtWookie

    Expert

    Jul 17, 2007
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    Motorola Semiconductor is now either ON Semiconductor or Freescale, I don't know which, but the Motorola name comes up in Freescale datasheets, and they both use the same part numbers, and they both have the same schematic in them. Texas Instruments' datasheet has a functionally identical circuit for chaining counters.

    Note that you'll only be able to count in one direction. If you want to be able to go the other way as well, you'd need to use something like a 4034 8-bit universal shift register instead.

    I've attached an image of the circuit that Beenthere is talking about.
     
  4. nanovate

    Distinguished Member

    May 7, 2007
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    Motorola's Semiconductor Product Division became Freescale. On Semi was an earlier divesture of a "power products" company that Motorola owned.
     
  5. Papabravo

    Expert

    Feb 24, 2006
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    I thought it included all of the discrete components like gates and transistors, diodes and such.
     
  6. nanovate

    Distinguished Member

    May 7, 2007
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  7. WVU Engineer

    Thread Starter Member

    Jan 18, 2008
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    the picture that SgtWookie has posted is a godd one. I have not tried it yet, but it does not make sense to me. Could someone please aid me in understanding how it works. This is what i see:


    The second chip in the series would only recevie a clock pulse when the first chips Q9 output goes high and the clock is high, this would disable the first chip for only 1 clock cycle and then the first chip would start over again. So basically the first chip would cycle through all 9 outputs a total of nine times before the third chip would even receive a clock pulse. Am i correct in how this appears to work. Correct me if i am wrong.
     
  8. SgtWookie

    Expert

    Jul 17, 2007
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    That is not correct.
    Assume that the leftmost 4017 has just been reset. This causes Q9 to be low, which is connected to CE\ and one input of a 2-input AND gate. Since CE\ is low, this counter can advance when it receives a clock pulse. Since one of the two inputs of the AND gate is held low, it's output will be low.

    9 clock pulses later, after advancing Q1, Q2... Q9 goes high. This also causes CE\ to go high, and one input of the 2-input AND gate to go high.

    The counter can no longer advance when it receives a clock pulse, because CE\ is held high via hard-wired to Q9; the only way to turn Q9 off is to toggle the RESET input (or cycle the power switch). However, the AND gate will now reflect on it's output the state of the clock input.

    The cycle is repeated with the 2nd counter, however the last counter is wired differently; it's CE\ is wired to ground, and it's Q9 is wired to the RESET input of the leftmost counter. Thus, when it reaches terminal count, it resets the first counter, which also turns off Q9 on that counter, which forces CE\ low along with one input to the first AND gate low, shutting off the train of clock pulses to subsequent counters. Q0 of the 1st counter is wired to the RESET of the 2nd counter, and Q0 of the 2nd counter is wired to the reset of the last counter, so when the 1st counter is reset, it forces the 2nd counter to reset, which resets the 3rd counter causing it's Q9 to drop, thus lowering the RESET input on the 1st counter.

    Does it make more sense now?
     
  9. WVU Engineer

    Thread Starter Member

    Jan 18, 2008
    15
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    Yes it does make more sense... for some reason i was thinking incorrectly, i was thinking that once the outputs reached Q9 it would automatically re-cycle, i did not take into account the reset pin, my apologize, i should have looked at the diagram a little longer before asking. Thank you for clearing me up though SGTWookie
     
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