capasitors behaving wierd..?

Discussion in 'Homework Help' started by Bombasa, Apr 15, 2013.

  1. Bombasa

    Thread Starter New Member

    Dec 2, 2012
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    I was supposed to do this labexperiment at school, but because of reasons i managed to miss it. The lab is closed so i have to do it simulated. :/

    My task is to graph the current of C1 and C2 when charging and discharging. I've put up 1ohm resistance on each the capasitors when uncharged and i get these results.

    Why is the current drop to 0 so fast through the capasitors compared to the voltage and current throught R1?
    It also looks like all the current and voltage travel through R1 instead of charging up C2?


    Am i missing something big here? Ive done similar experiments before, like RCseries, RLC and RL circuits, but this one is confusing the hell out of me!

    [​IMG]
     
  2. Jony130

    AAC Fanatic!

    Feb 17, 2009
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    Hm, I think it is a classic example of a GiGO.
    How can you see discharge on the plot if R1 discharge current is very small (5.5uA) in comparison with 5A charging current?
    Also add simulation file.
     
    Last edited: Apr 15, 2013
  3. Bombasa

    Thread Starter New Member

    Dec 2, 2012
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    0
    I dont understand your question..

    I uploaded the file though. Added it as an attachment.
     
  4. Jony130

    AAC Fanatic!

    Feb 17, 2009
    3,957
    1,097
    C1 and C2 capacitors end the charging phase at about 140us after simulation start.
    Then C2 start to discharge with a very low current in comparison with a charging current. So when you plot this charging current (5A) in LTspice, how can you want to see discharge current (5uA a million times smaller than charging current) on the same LTspice plot? There is a huge difference in plot scale. And this is why you can not see a discharge current.
     
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