If you have a capacitor in series with a ciruit, once the capacitor fills up, no more electricity will flow in the circuit...correct? Or is this wrong.

 

The more proper term is "becomes fully charged", but the cessation of current at that point is correct. That is why we say that capacitors block DC.

 

so that being said. In this 555 timer astable circuit(or any for that matter):

Is that why the threshold and the trigger are able to see the flucuations in voltage? Because as the Cap charges the voltage in that portion of the circuit changes? As in the power stops coming for the Battery?

I guess that might be hard to understand. To clarify, I was always confused as to how the threshold and trigger could know the voltage was changing because I thought the 9volts would still be coming from the battery through R1 and R2.

 

That is not the case for C1. There is an internal voltage comparator that trips when the voltage on the timing capacitor has reached 2/3rds Vcc. An internal switch puts pin 7 to ground to discharge the capacitor. When the level is far enough down, the switch turns off, and C1 starts to charge up again.

Get a data sheet for a 555. It has a description of how the IC works.

 

Hello,

I see you took the picture from antoon's website:
http://www.uoguelph.ca/~antoon/gadgets/555/555.html

When you read through the page you will see how the charging and discharging happens.

Another example of an oscillator that uses charging and discharging of a capacitor is the relexation oscillator:
http://www.falstad.com/circuit/e-relaxosc.html

Greetings,
Bertus

 

i don't think I explained myself well enought. I know how it charges and discharges. I get how it functions. My question was about why the threshold and trigger "see" the voltage of the capacitor and not the 9v through the resistors. Maybe some pics will help.

Like is the reason the trigger and theshold pin don't "see" the 9v because when the cap is full no current flows?
Because if not wouldn't the current continue to through r1/r2 to ground through C1 and then the theshold and trigger would see the 9 the whole time.



I guess what I'm trying to see is how is it able to Monitor the C1 voltage without the voltage coming from the battery through R1/R2 getting read?

 

Hello,

Does this page give a better explanation?

http://www.ecircuitcenter.com/Circuits/555_Timer1/555_timer1.htm

There are two comparators connected to a flip-flop that controls the discharge transistor.

Here is also an applet to show it:
http://www.williamson-labs.com/pu-aa-555-timer_med.htm

Greetings,
Bertus

 

I really must be over looking something. I think I get why the trigger works. But how/why does the threshold not see the voltage from R1/R2(Ra/Rb) and only the voltage from the C1. I have a feeling I'm thinking abou this the wrong way.

Is it because when the cap fills up the current stop flowing through R1/R2 to the cap(as answered by my very first question that caps block DC current) so the only voltage the threshold can "read" is the voltage from the cap?

Sorry for being dense.

 

Hello,

During the charge state the discharge transistor is not having any current.
The voltage of the capacitor is the input to BOTH comparators.
The comparators have different comparison levels.
The lower one (trigger) is at 1/3 VCC, the upper one (threshold) is at 2/3 VCC.
In the applet you could see the trigger starts the "fill" cycle and
the threshold starts the "release" cycle.

Greetings,
Bertus

 

Hello,

During the charge state the discharge transistor is not having any current.
The voltage of the capacitor is the input to BOTH comparators.
The comparators have different comparison levels.
The lower one (trigger) is at 1/3 VCC, the upper one (threshold) is at 2/3 VCC.
In the applet you could see the trigger starts the "fill" cycle and
the threshold starts the "release" cycle.

Greetings,
Bertus

Yep, I understand that

I wish I could think of a clearer way to explain what I am asking. In my mind it seems clear, but either I am asking a question that makes no sense or I'm not asking it correctly.

 

Hello,

There will be hardly no current (some micro amperes) flowing into the comparators.
The comparators can "see" the voltage of the capacitor without influecing the voltage on the capacitor.
"All" the current from the resistors (Ra+Rb) will flow into the capacitor during the "fill" cycle.
"All" of the current will flow from the capacitor through Rb and the discharge transistor to ground during the "release" cycle.

Greetings,
Bertus

 

"All" the current from the resistors (Ra+Rb) will flow into the capacitor during the "fill" cycle.

Ok. As it's flowing into the capacitor, how does the threshold pin not read that Voltage?

There would be be 9volts going through Ra/b into the cap right? So why why doesn't the comparator no recognize the 9volts coming through there?

--------------

Look at this pic of the simulation that I edited.



Why at this point does the threshold have nothing on it. Shouldn't it be seeing whatever is coming through Ra/b down to the cap?

I'm not saying the simulation is wrong, because I know this is how it's supposed to work, I want to know why. Because in my mind if it is 9volts coming through Ra/Rb then the threshold should see that. Obviously i know it doesn't though.

 

Hello,

The threshold only sees the voltage of the capacitor.
The capacitor delays the voltage coming from the 9 Volts through the resistors Ra+Rb.

Greetings,
Bertus

 

Hello,

The threshold only sees the voltage of the capacitor.
The capacitor delays the voltage coming from the 9 Volts through the resistors Ra+Rb.

Greetings,
Bertus

Ok, good. Thats what I was trying to get at.

Is the reason the 9v is delayed is because of the whole Capacitors block DC current as the fill up thing that I asked about right away?

 

Hello,

The resistance of R(1)a+R(2)b together with the capacitor give the delays.

You can calculate t1 and t2 times with the formulas below:

t1 = .693(R1+R2)C, t2 = .693 x R2 x C
T1 is the "fill" time, T2 is the "release" time.

Greetings,
Bertus

 

Hello,

The resistance of R(1)a+R(2)b together with the capacitor give the delays.

You can calculate t1 and t2 times with the formulas below:

t1 = .693(R1+R2)C, t2 = .693 x R2 x C
T1 is the "fill" time, T2 is the "release" time.

Greetings,
Bertus

Right

But what exactly is the cause of the delay in voltage. Is it the DC blocking aspect of the Cap?

 

The capacitor is there to accumulate charge at a predictable and repeatable rate. It charges through R1 & R2 in series. It discharges through R2 through the switch in the 555.

Have you read about how a 555 timer IC works?

 

R1 and R2 do not apply 9V to the capacitor. They apply a small current that slowly charges the capacitor.

 

The capacitor is there to accumulate charge at a predictable and repeatable rate. It charges through R1 & R2 in series. It discharges through R2 through the switch in the 555.

Have you read about how a 555 timer IC works?

Yes I know how it works. I thought maybe it served a dual purpose.

R1 and R2 do not apply 9V to the capacitor. They apply a small current that slowly charges the capacitor.

Why does 9v not go through R1/R2?

 

vindicate,

f you have a capacitor in series with a ciruit, once the capacitor fills up, no more electricity will flow in the circuit...correct? Or is this wrong.

You might find this link enlightening, especially post #3. http://forum.allaboutcircuits.com/showthread.php?t=12808

Ratch