Hello

I am looking for how distance I can locate 'decoupling capacitors' from loaded device in same layer on a board.

Is there any fomula for it and description?

Thanks

 

Hello

I am looking for how distance I can locate 'decoupling capacitors' from loaded device in same layer on a board.

Is there any fomula for it and description?

Thanks

General rule of thumb....as away as possible from the heating element....

 

General rule of thumb....as away as possible from the heating element....

Thx your opinion.

But I know the general rule of thumb what you said.

I meant the exact formula related to impedance, resonan frequency
,Er or so on...

Thanks.

 

There is no exact formula to suit all situations.

 

in the old days, we used to use the outside foil of caps to ground. I suppose if you chose the ground side of the cap to be nearest the signal side it would work the same.

 

The rule is As close as physically possible. The purpose of the capacitor is to lower the effective source impedance of the power supply at the point it powers the chip. To this end, the capacitor acts as the shunt leg of a low pass filter, with the series leg formed by the trace from the cap back to the ps and the supply's own outut impedance. From the cap to the chip, any trace length adds resistance and inductance, both of which raise the effective impedance. So how close varys depending on the frequencies of interest in the circuit, and the tolerance of the chip for non-zero power source impedance. For example, voltage feedback video opamps are surprisingly well behaved despite very wide bandwidth, while current feedback opamps are very fickle about decoupling. Also, audio power amp chips, especially older ones like the TDA's from Europe, are notorious for breaking into oscillation at a few hundred KHz even with "pretty good" decoupling.

ak

 

It also depends on your board layout. It's important to have low inductance from the decoupling to the IC. So if you have 2 big ground planes with there own distributed capacitance you can be further away than if you just have 2 traces for power and ground.

 

For best decoupling, use a surface mount capacitor chip with the ground side going directly to a ground plane (not through a via) and the other side going to a pad as close as possible to the power pin on the device being decoupled. Have the power pin on one side of the capacitor pad and the power line on the other side of the pad (so the device current has to go through the pad). This minimizes the lead inductance to the capacitor.

 

Thanks all above!

I have been looking for the fomula about how distance I should locate the decoupling capacitors.

= charge propagation velocity/(coefficient*2*pi*Fsrf[Self Resonance Frequency])

Would you reckon it is reasonable?

Thanks

 

Thanks all above!

I have been looking for the fomula about how distance I should locate the decoupling capacitors.

= charge propagation velocity/(coefficient*2*pi*Fsrf[Self Resonance Frequency])

Would you reckon it is reasonable?

Thanks

I know of no "formula" for this. Typically you locate the capacitor as close to the devices power pins as physically feasible.

 

Everyone say "Decoupling capacitors should be as close as the devices power pins as physically feasible.". I know this simple theory. But we are also curious for how distance we could/should locate them or not when there is a limited space of our PCB.

Thanks