Cap on cmos input?

Discussion in 'The Projects Forum' started by Gadersd, Apr 24, 2014.

  1. Gadersd

    Thread Starter Member

    Dec 8, 2012
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    It it common to place a cap on a long input on a CMOS ic. If so what size cap should I use? The wire will be approximately 5 feet long at max.
     
  2. AnalogKid

    Distinguished Member

    Aug 1, 2013
    4,542
    1,251
    A cap can absorb induces transients, but not quickly. Also, it slows down the transition edges of the logic signal. If that's ok, especially with a resistor in series with the cap, then it is very low cost protection. For protection with way better speed, use two Shottkey diodes, one to Vdd and one to Vee. Faster clamping and almost no capacitive loading.

    ak
     
  3. joeyd999

    AAC Fanatic!

    Jun 6, 2011
    2,689
    2,750
    I shook my Magic 8 ball, and it said "Reply hazy, try again". So I did.

    Then is said, "Without a doubt," followed by "Outlook not so good" on the third try.

    You did not provide nearly the amount of information required to answer a question like this.

    What is the 5 foot wire attached to?
    Is it analog or digital?
    What is the frequency range of signals you are trying to input/capture?
    What is the environment in which the device is used?
    Are you having any problems with your current design? If so, what?

    Provide a schematic of what you are trying to do, please.
     
  4. Gadersd

    Thread Starter Member

    Dec 8, 2012
    98
    1
    It is a digital signal that is attached to the output of another cmos chip. The frequency is approximately 1000 hz.
     
  5. Alec_t

    AAC Fanatic!

    Sep 17, 2013
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    Does the CMOS chip receiving the signal have a Schmitt trigger input?
     
  6. Gadersd

    Thread Starter Member

    Dec 8, 2012
    98
    1
    I do not need the cap for protection, but for smoothing the potentially noisy cmos input. No, there is no Schmitt trigger input.
     
  7. Alec_t

    AAC Fanatic!

    Sep 17, 2013
    5,801
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    Which IC is the receiver? Slugging the signal with a cap may make it unsuitable for clocking any IC which relies on a sharp pulse edge.
     
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