cable for Digital signals

Discussion in 'General Electronics Chat' started by masudasim, Jan 2, 2013.

  1. masudasim

    Thread Starter New Member

    Jul 10, 2010
    Hello all

    i am using FPGA board with ADC Ic and i have to provide clock signals (>40 MHz) from FPGA to ADC and digital output signals from ADC to FPGA.

    What type of cables should i select for digital clock/data?

    How much length of above cable i can use or in other words how far FPGA board can be placed from ADC board without clock distortion?

    Please help me

  2. Brownout

    Well-Known Member

    Jan 10, 2012
    Use a minature SMT coax connector and cable, if possible. The length should be a few inches. I don't know the max length, but you should be good up to 12" or so. I suggest some experimentation with the cable. You might also be able to use an analog simulator with the calbe's parameters to ascertain the maximum length.
  3. crutschow


    Mar 14, 2008
    For any significant length, digital signals are often sent as a differential pair on ribbon cable or twisted pair wire using LVDS drivers and receivers. This minimizes signal distortion and noise.
  4. Brownout

    Well-Known Member

    Jan 10, 2012
    Hi again,

    My previous answer was for the clock signal. Didn't read the question completely. I agree that data can/should be sent as a differential signal over a ribbon cable. Use adjancent pairs of wires for the differential signals, and seperate each pair with one or two wires connected to ground. Leave the outer wires connected to ground.
  5. Papabravo


    Feb 24, 2006
    The original question was how far can you go WITHOUT clock distortion. Regardless of what you do there is going to be some distortion so the simple answer is "zero". Practically speaking there are three main things to worry about.
    1. IR loss in the cable. This happens in a mainframe computer system where the disk drive may be several tens of meters away from the CPU.
    2. Reflections and impedance discontinuities. This is the tough one to detect, understand, and prevent.
    3. Skew between the clock and the data lines if this is a parallel interface.
    Without more details it is hard to know what your requirements might tell us; if one or all of these will be a major problem.