Logic.ly has some peculiarities. Add outputs (lamps) to the rightmost gates and use switches instead of hard coding the inputs. See if that helps.

 

The problem with simulating a latch is that the simulator doesn't know how to deal with an undefined signal, so until a signal is forced into an unambiguous state that is independent of any possible value of any currently undefined signals, it will remain undefined. In actuality in this case, the constraints on the relationships between the undefined signals is sufficient to resolve the system and an analog simulation of this circuit would resolve itself just fine, but I'm not aware of any logic simulators that do a good job of looking at larger circuit level constraints (they may exist, though) but, instead, only look at the signals on a device by device level.

The usual way to resolve this is to provide the simulator with an initial condition for key nodes. In this case, if you provide an initial condition for one of the feedback nodes (i.e., one of the latch outputs) that should do it. If you don't have the ability to specify initial conditions, then you can fake it by inserting an OR gate in one of the feedback paths and applying a RESET signal to the other input that is pulsed HI at the beginning of the simulation and then remains LO after that, effectively removing it from the circuit.

 

Ok so It's not the design but the simulation. Regardless, next step is replacing the 3NAND's with equivalent 2NAND's

This time the system does resolve even though it's basically the same (unless I screwed up) The 3 2NAND's clusterd closely together on the top and bottom half are the simulated 3NAND's.

This is the JK-FF part of the flipflop. Should I now try to (seperately) build the D-FF flipflop?

 

Are you SURE that this works? Aren't you indicating that BOTH output's of the JK FF the same? Is that every supposed to be the case?

It's not enough for the system to resolve, it must also be correct!

Look at your subcircuit for your 3-input NAND gate. While I can make a 3-input AND gate by putting two signals into one AND and the output of that into a second AND along with the third signal, does that work for a NAND?

Build up JUST a 3-input NAND gate from 2-input NAND gates and thoroughly test it to make sure you are doing it correctly.

 

Alright, once more. I re-did the flipflop. I double checked the 3NAND replacement before I implemented it. As long as the imputs aren't 1 1 1, the output is 1, just like a normal 3NAND. The system also doesn't resolve, just like the flipflop before.

 

That looks much better. You still have the same problem as before regarding resolving initial conditions. If your simulator does not permit you to specify an initial condition on a node, then add a an appropriate gate to allow you to apply a reset signal to force the initial condition. I described how to do that in an earlier post.

 

Logic.ly doesn't allow setting initial conditions. That's why I suggest all inputs be switches and to cycle them once at the start of the simulation.

 

Logic.ly doesn't allow setting initial conditions. That's why I suggest all inputs be switches and to cycle them once at the start of the simulation.

That may or may not resolve ambiguous internal nodes -- I suspect it won't in this case since establishing a SET condition doesn't. Better to resolve the ambiguity with a transient reset signal.

 

I could resolve the system using WBahn's method but it's not particularly important that it works in the simulation. I have to build the entire flipflop with actual gates (negating the resolve issue) So now I need to build the d-ff part of the system

 

Actually building it in hardware is usually the better learning experience, anyway. I'm glad you're being expected to do that.

 

Ok I build the d-ff flipflop. I followed this image

I ended up with this. The sideways nand is the inverter, the switch = d

When hooking these flipflop together, this is the result. They now have a shared clock.

Please tell me this is correct

 

At first glance it looks okay. Why don't you just build it and test it out?