# Buffers and communications

Discussion in 'Wireless & RF Design' started by pandya, Mar 28, 2008.

1. ### pandya Thread Starter New Member

Mar 28, 2008
5
0
please will you tell me what is the problem with buffer at high speed. As we can put a large size of buffer theoritically and solve this problem of synchronisation, cant we?

Apr 20, 2004
15,815
283
3. ### Papabravo Expert

Feb 24, 2006
10,340
1,850
That is a big maybe. If you have two continuous syncronous data streams, and they run at different rates you can prove that no buffer, no mater how large, will prevent the faster channel from exhausting the available data. In the other direction the faster channel will eventually fill the buffer.

The only way a FIFO buffer can help is if there are gaps in the syncronous transmission. Then you need to ensure that the buffer is large enough to hold a burst transfer from one side without overflow or underflow.

4. ### studiot AAC Fanatic!

Nov 9, 2007
5,005
515
Since we seem to have moved house and have left the benefit of the old foundations parhaps Pandya would like to expand on her(?) question.

Is this buffer proposed for serial or parallel transfer?

A few rule of thumb figures are in order.

Allowing for the actual speed of real signals through cables or circuit board tracks we have:

The signal travels about 100mm in 1 nanosecond, (corresponding to 1Ghz in the frequency domain).

Consider two signals which start together but one travels 10mm further (the distance across a chip). This will arrive 0.1 nanosecond after the first pulse.

So draw a timing diagram for a 1 GHz processor, clocking 0.2 nanosecond pulses every nanosecond.
Include space for the clock and handshaking pulses.

You will see that processors at or above 1Ghz are approaching the transmission limit.

5. ### Papabravo Expert

Feb 24, 2006
10,340
1,850
Well that's two kinds of buffer. Do we actually know which one he is talking about. I interpret his question about "size" as implying a "data buffer" and opposed to a "buffer amplifier"

6. ### beenthere Retired Moderator

Apr 20, 2004
15,815
283
I have just gone through the thread this came from, and can't make any sense of where the buffer and synchronization idea comes from. We need the OP to come back on this one.

7. ### pandya Thread Starter New Member

Mar 28, 2008
5
0
oh Thanks for this nice responce i have asked this on too many sites but i dont get satisfied answere any were. this site is really nice one.
here i am talking about "data buffer" and I am asking for parallel transmission.
I want to know if this buffer concept will useful at higher transmission rate or at high rates data received at receiver will be garbage only?
And I have little low information of these basic things as i am new in this field so can you discus in more detail how data becomes garbage in transmission line, in parallel, at high transmission rate?

8. ### Papabravo Expert

Feb 24, 2006
10,340
1,850
The lack of a satisfactory answer is partly due to the vague and ambiguous nature of the original question. Let me try to clarify. You are interested in the behavior of parallel data transmission systems where the data rate is high enough for several bits to "exist" on the cable at one time. Under those conditions small changes in the physical environment can cause the bits on parallel channels to be skewed with respect to one another. Working on the disk drive standards committee in the 1980's we wrestled with this problem and it is a head hurter. The conclusion was that clock signals traveling on the same cable were desirable. They could be interlocked or they could simply be used to count transactions. For example if I send ten words down the cable with ten clock pulses, I expect ten clock pulses to be returned. This techniques falls apart if there is too much difference across the conductors of the cable. I'm not sure if they ever came up with a really good solution.

9. ### studiot AAC Fanatic!

Nov 9, 2007
5,005
515
Let's work through this a bit at a time.

Think of yourself as a designer of a data transmission system and ask yourself how you are going to do this.

First we agree that the data will be in binary form. This requires two states to represent it.

Then we choose an electrical setup which can present two states.

One possible scheme is to choose two voltage levels, say 0volts=0 and 5volts=1.

Now consider two devices connected by some form of link. One device sets the voltage level and the other detects it.

Questions to resolve

How will the second device know when to detect the voltage level?

How long should it wait before it can expect a second data bit?

How will it know that the second detection is a second bit, not the end of the first, or the beginning of the third, because the second was a trifle short?

Have you followed this so far?

It would also help match time zones to know where in the world you are.

10. ### Papabravo Expert

Feb 24, 2006
10,340
1,850
So far so good.

Now the main environmental factors to consider are the length and diameter of the cable and it's characteristic impedance.

The length of the cable and the diameter of the conductor will tell us if we have a problem with IR-losses or with common mode voltage differences.

The rise time, fall time, and pulse width will give us a clue about the impact of reflections on the cable.

Now we can talk about the effect of skew on multiple parallel conductors.

Of course this is overly simplified, but at least we can determine if we are in the right church and sitting on the same pew.

11. ### beenthere Retired Moderator

Apr 20, 2004
15,815
283
One old way out is by means of interlocked handshakes. The receiving device gets an ODR (output data ready) signal when the data frame is present on the cable. It sends an ODA (output data acknowledge) back to signal that it has latched the data.

Ultimately, the transmission speed depends on the length of the cable. Even with differential pair signaling, it takes time to be certain the data is present and correct when the ODR arrives. The cost of the hardware and cabling is just prohibitive compared with serial. To do 32 bits in parallel, you have to duplicate all 32 lines that could support the serial bitstream, plus add the handshake lines. That's an extra 4 twisted pairs, as you have to handshake both ways.

12. ### pandya Thread Starter New Member

Mar 28, 2008
5
0
ok I asked this question on different thread so it might be confusing let me clear my question.
i was serching resons why parallel is replaced by serial now a days as parallel is faster then serial.
I read answere of it given by "studiot" on other thread as:

::
The problem with parallel transmission is that although you can send many bits at once (yes 8 in many systems) receive 'at once' is not a true statement.
Each bit travels a slightly different path down the cable and to a different pin on the chip.
The small differences in path length that each bit travels becomes more and more significant as speed increases. Thus the bits are not all received together.
As a first step you can counter this by holding the bits in a buffer until all are received (thereby loosing some of your speed gain), but eventually the bits become so out of step that garbage is received. This effect limits the max speed at which you can transmit parallel data
::

And i get my answere as studiot said to draw timing diagram, i knew from it that in parallel at high speed data received at other end will be garbage , so though we place buffer it will not become useful.
Thanks to all

13. ### studiot AAC Fanatic!

Nov 9, 2007
5,005
515
Now we are getting somewhere.

I assume you have realised that from post#9 that if you use voltage levels for signalling you also need handshaking/ control lines. These, of course, suffer the same delays and propagation restrictions as data lines.

So the time to transfer a unit of data must include the handshaking time.

Now consider if we change the representation so that all data bits are zero unless specifically set to 1.

To send a 1 setting we send a single transition and the second device now detect the transition, not the level. Each time it detects a transition it sends a 1 into a shift register (FIFO buffer) so the data builds up serially.

So long as a transition does not arrive within the dead time of device 2 it does not matter how long or short the wait between transitions is or how variable. The cost of this scheme is that we now need start and stop bits to signify when data is actually being transmitted and perhaps some error checking bits as well.
Modern computer memory - double data rate or DDR memory uses both up and down transitions to increase the transfer rate.

So far I haven't explicitly distinguished between serial and parallel. This is because real world applications use a mixture for best results.
Parallel communications should really be called bit parallel, byte serial.
Modern memory chips are read by sending a series of parallel address information by reading a row serially in bursts within each parallel cycle.

If you are still with me post again for the next installment.

14. ### pandya Thread Starter New Member

Mar 28, 2008
5
0
Yes studiot i get idea of timing diagram from post #9. And i have also considered the control signal.
I think this problem of delay is reffered as timing skew, Am i right?
And as you said problem is that data does not arrive in dead time. Now please can you tell me that how start and stop bits will be useful in this scheme?

15. ### studiot AAC Fanatic!

Nov 9, 2007
5,005
515
I'm doing this a small chunk at a time because it's important to get a good hold of the concepts before going on to put them together.

Remember that with serial communication you do not need handshaking lines. the receiver waits an indefinite time for the next transmission, this may be milliseconds or days. When the receiver detects a change (level or transition) it needs to know the answer to the question.

Is this the start of data? Or is it just a spurious pulse, from an event downline somewhere?

This information must be contained within the pulse stream itself.

If we send, say three ones in a row (1,1,1) the receiver can be programmed to accept the next 8 pulses as a valid data byte. Further pulses can then represent error checking (parity) and finally stop bits to definitely indicate the end of transmission. These extra pulses (start and stop) are called framing pulses.

Once you got hold of the idea that each method of data representation (I have only mentioned 2, there are many others) presents its own special problems and requirements,
we can move on to cover your query with the buffers.

16. ### pandya Thread Starter New Member

Mar 28, 2008
5
0
My querry was only that can we solve this problem of synchronization using buffers or not?

And i understand that buffers can give little more time for well transition untill they are not filled by faster transmission line. As we use large size data buffers we can get littel more time but after some instance buffer will be filled with data by fast transmitter and become full, our problem will not be solved.

If we any how can manage data transfer, but then same problem will occure with control signal. And i think that to manage both( may be we cant manage single one also) is not truly possible.

Actually i am student in engineering , and i am working with project of serial protocol. but i was having question that as parallel are faster then serial then why they cant achive faster rates now a days as i see figures on different sites related to parallel SCSI and SAS, SATA and PATA. From that study this queston arrise in my mind.

If you have more things which you think can be useful for this then i will alsways like to lern them(Specialy if we can solve this problem by start and stop bits, with data or we can use address to each packet then receive them independent as i think it also not useful).