# buck or boost converter derivation of output voltage

Discussion in 'General Electronics Chat' started by jdessino, Jul 22, 2011.

1. ### jdessino Thread Starter New Member

Feb 11, 2009
2
0
Hi all, this is my first post to this forum.

I have been deriving the operation of ideal buck and boost converters using Fundamentals of Power Electronics by Erickson and Maksimovic and have a few questions.

For reference, here are links to pictures of the ideal circuits.
Buck converter:
http://www.mathworks.com/matlabcentral/fx_files/18833/3/content/html/buck.png
Boost converter:
http://www.mathworks.com/matlabcentral/fx_files/18833/3/content/html/boost.png

For either the ideal buck or boost, when you solve for the output voltage how do you know that the DC component will be the same when the switch is open and when the switch is closed? Is it held at the same voltage in either stage by the cap?

What I mean is that if I call the DC output voltage V1 during the switch open phase and V2 during the switch closed phase, how do I mathematically prove that V1 = V2 in one complete switching cycle?

I guess this also leads into the question of how does one know the inductor current/capacitor voltage will eventually enter a steady state?

Thanks! Any help is much appreciated!

2. ### t_n_k AAC Fanatic!

Mar 6, 2009
5,448
783
In either case of the buck or boost converter mode the capacitor voltage is continually varying between certain limits subject to the operating mode (continuous or discontinuous inductor current), loading and duty cycle.

At steady state operating conditions the mean DC capacitor voltage (& hence output) will have a constant value. However, this mean value has a superimposed ripple voltage due to the switching action. The design process in part involves reducing the ripple to an acceptable value. So strictly speaking the instantaneous output volatge is not constant even at steady state operating conditions.

3. ### jdessino Thread Starter New Member

Feb 11, 2009
2
0
Right, I understand that there will be ripple due to the switching frequency as well as transients from the capacitor's time constant. I also realize that the mean output voltage should be constant, whereas the actual output voltage will not, and take the form of a triangle or sawtooth waveform. I probably should have put "mean output voltage" instead of the "DC component of the output voltage," sorry about that.

I also should have stated that this was for continuous current mode.

When I solve the circuits for the "charging" stage and the "discharging" stage the mean output voltage only seems to definitely be equal in both stages if I assume steady state operation.

But how can I assume that? How can I prove that the output voltage rise during one state of the switch duty cycle will be equal to the output voltage decrease during the other state of the duty cycle? I guess I am asking if it comes out in the math or not, and if so, where.

Hopefully that was a little more clear. And thanks again!!

4. ### steveb Senior Member

Jul 3, 2008
2,433
469
I'm not sure if I'm understanding your real question. The key thing about the coil current and the capacitor voltage is that the are both variables that will not change instantaneously because they are system states. This means that their time evolution is described by equations that look something like ...

dVc/dt = f1(vx ... ix)
dIL/dt = f2(vx ... ix)

Since derivatives should not normally equal infinity, you can be sure these variables tend to change gradually, while other system variables may very well change very fast (coil voltage and capacitor current, for example). The slow (non-instantaneous) changes of the states allow you to know that ...

1. they will be held equal through the switching transitions (that is equal just before and just after the switching point).
2. they typically/often will not change too much over short time scales (for example one cycle in continuous mode)
3. they should reach a steady state condition once the time derivatives go to zero (in an average sense over a cycle), which requires constant conditions and waiting much longer than the system time constants.
4. steady state will mean that the capacitor voltage and coil current will be the same after each cycle. (that is, there is ripple, but the ripple is fixed relative to the switching period, and always cycles back)

This last point means that not only is the voltage held equal through the swichting transistion, but in steady state, the voltage always comes back to the same value at each consecutive cycle. That can be useful in simplifying the analysis.

Last edited: Jul 28, 2011