Hello,

I'm using a monolithic current-controlled buck regulator IC (i.e. LTC3633A) which integrates an OTA error amplifier and expects an external type II compensation network to stabilize the supply. I don't have any feed-forward compensation stuffed. A curious characteristic of the phase response for this chip is that it dips quite close (~16 degrees) to zero for a 5kHz wide shelf well below the unit gain crossover (fc) frequency. The phase margin at fc is good at ~60 degrees, but I'm wondering if the low frequency dip is indicative of borderline conditional stability even though it hasn't dipped all the way to zero. I can't seem to find technical address of this online.

The gain-phase plot (attached) was obtained at room temperature with a single sample. I've used the Venable method to design the compensation pole/zero and the measured results are as expected. I designed for 60 degree margin and I hypothesize that I can readily lift the 16 degree shelf by increasing to 70 or 80 degrees, which would widen the pole-zero pair, but I'm trying to figure out if I have a stability problem in the first place. At 40kHz, the crossover is not aggressive at all, so I don't think that's the problem. It just seems like the plant phase lag is dominating earlier than expected.

fs=1MHz, K=3.732, fc=40kHz, fz=10.7kHz, fp=149kHz.

Any thoughts?

Thank you in advance,
GuruInTraining

 

The loop may not oscillate due to the 15 degree phase margin but it could give overshoot and ringing in the regulator's response to a step change in load current.

 

The loop may not oscillate due to the 15 degree phase margin but it could give overshoot and ringing in the regulator's response to a step change in load current.

Thanks crutschow. I am going to supplement the gain-phase analysis with load step characterization as well. Do you think the combination of the two will be necessary and sufficient to ensure stability?

 

Thanks crutschow. I am going to supplement the gain-phase analysis with load step characterization as well. Do you think the combination of the two will be necessary and sufficient to ensure stability?

I would think so.
That's the two criteria I used for the buck regulator I designed some years ago.

 

Here are my thoughts...

You're screaming down at 40dB/dec almost through the entire plot. I'd try to move that zero (@ 20kHz) down to 200 Hz... that will increase you open loop bandwidth and pull that 15deg shelf up to 90 degrees - where it should be. At a minimum I'd be putting the zero a decade before the 0dB cross-over (~3kHz).

I personally think the 15 degrees is a problem. Remember - the definition of instability is to have gain when your phase crosses 180deg - and you're dangerously close to that. I would be doing everything possible to get that to be at least 30 degrees, but preferably 45+.

If you do decide to build like this - I would put the product through its paces before I let it ship. Step loading the supply at 1.5kHz 50% duty cycle over temp and humidity would be a must.

 

Hi tindel. Thank you for your input!

A few clarifications. The crossover is presently at about 38kHz not 3kHz and the zero is at 10kHz. I used the Venable method to locate the pole and zero at the geometric mean of the desired fc according to the desired phase margin. So i'm getting the expected phase margin of 60 degrees at fc per that design procedure. Therefore, this seems to imply that perhaps I'm trying to push fc out too far. I've designed fc at 40kHz as a general recommendation from Linear Tech to not push past 50kHz for best noise immunity. I'd prefer to not compromise the response performance by moving it too much to the left.

It is interesting that even with this pole/zero location there doesn't seem to be any flat gain region from the zero between 10kHz and 140kHz. Also, I don't understand why I'm getting ~40dB slope when the integrator is the only loss contribution below 10kHz.

Don't worry, I don't ship anything questionable. This response will be textbook before it heads over to Design Validation.

 

The plot you've shown is anything but textbook.

What I meant to say is that I would shift the zero to the left so that it would be at about 3kHz - at a minimum - and preferably at 200Hz to get a nice 20dB per decade slope through the entire plot.

I took a closer look at the datasheet. I realized that this is a current mode feedback topology. All of the current control is internal to the chip and you have no way to measure your inner loop. You can only view your voltage control loop - or the total of both control loops. I'm also curious why you are seeing -40dB the entire way down. I don't think you've broken the loop properly. Can you post a schematic showing exactly where you've broken your loop? and maybe take a picture of your measurement method. And provide a scope plot of your input and output waveforms while the venable is operating at a couple different frequencies? http://www.ti.com/lit/an/snva364a/snva364a.pdf <- This is a good app-note that shows the proper method for measuring your open-loop gain of a buck converter.

Who at LT is giving you the advise to keep your open loop bandwidth below 40kHz? Is this advice out of a datasheet or app note - I'd be curious to understand their logic in that comment. Typically you want your open loop bandwidth to be as high as possible but no more than a factor of 10 less than your switching frequency. This means that you could be controlling the output voltage at up to ~225kHz (Assuming your switching frequency has been set at 2.25MHz) for this power supply

A Venable is a brand of Frequency Response Analyzer (FRA) - not a method - so your multiple references to this being a method has me a bit confused. I don't believe you're using a venable brand FRA... I would be curious what brand you are using though - as I'm in the market to get one.

 

Actually -- I just realized that the current loop is probably operating at about 220kHz - so the voltage feedback shouldn't be more than about 40kHz.

 

I understand the plot as posted is anything but textbook. My point was that I will fix it so that it looks textbook before the design gets released. ;-)

I figured out to -40dB/decade issue yesterday. The current mode control mostly cancels out the output inductor so the output filter becomes the load capacitance in parallel with the load R. This contributes the second -20dB/decade and -90 degrees at the output RC knee. So the general shape of the slope, notwithstanding compensation will be -40dB and cannot be changed (again, outside of the influence of the compensation). Again, due to the integrator + output RC.

I agree that I can shift the zero left to hopefully improve things. I'm going to try that today. I've been having trouble with repeatability of measurement with this chip. Two of us here are about to transition over to working with the LT development board exclusively to try to reproduce the problems we are seeing measuring on our hardware.

On the measurement front, I can and have measured the plant from ITH to output as well as the closed loop from divider stimulus to output. The chip interface provides for this. Venable is a brand of instrument but they publish a wealth of information on how to both optimally design compensation up front (instead of using the tweak and test method). There are about 15 app notes on their website. So the technique I am using is published across several of their papers. I am using a Keysight E5061B Network Analyzer for my measurements.

I have high confidence in my measurement setup and we have a second person here duplicating my efforts. I'm doing the standard WB isolation transformer injection across a 100 ohm resistor between the output and high side feedback divider resistor. In the case of measuring the plant, (REF) is connected to the ITH pin and (TEST) is connected to the supply output. In the case of closed loop, (REF) is the low side of the injection resistor and (TEST) is the supply output. In all cases, (TEST) as viewed on a DSO (in parallel) is a clean sinusoid across all frequencies of interest. So I know the stimulus and injection methods are OK. Note that in the above plot I've gone even further to scan each decade individually with its own power level to ensure distortion-free stimulus within each decade and then appended the results.

The LT advice is respect to the closed loop BW, not open loop. They are saying not to push the fc beyond 50kHz for best noise immunity. Incidentally, I received notice from their factory yesterday that, "It's OK to have the phase droop like that before fc. The system can still be very stable."

At the limit of my present understanding, it seems like unity gain at 360 phase is singularly bad but other closely related situations seem non-intuitively OK . For example, if unity gain at 360 results in oscillation, wouldn't 2dB gain at 360 result in oscillation at increasing amplitude? Similarly, if the phase is close enough to 360, but not exactly 360, wouldn't a very high gain (as is present in my above plots) also be likely to cause oscillation? These are some of the technical points I don't exactly have clarity on, and hence the original reason for my post here.

 

It sounds like you're understand the problem well and that your setup is probably correct. Repeatability can be difficult when taking these types of measurements. Remember you're looking at a HUGE dynamic range - nearly 6 orders of magnitude! Sometimes it can be helpful to test at different injection voltages for different frequency ranges and to cut and paste the results in a excel or a photo editor or something.

crutschow's advice in post #2 is spot on with the plot you posted. You'll probably see excessive ringing in the frequency range where the phase dips - but probably not outright oscillation. The frequency is low enough that most designs are not well decoupled for that frequency band. Hence, my advise to try step loading it at the frequency where the phase dip is lowest to try to bring out the ringing. Step loading at lower frequencies can work too if a odd harmonic falls within this frequency range. My rule of thumb is to have more than 30 degrees of phase margin and 6dB of gain margin.

I assume you are having trouble on a board that I assume this power supply is powering. Have you narrowed down the issues to the power supply for sure? Have you seen any ringing in the power supply?

Always take your apps engineer and sales guys information with a grain of salt. They are paid in how many parts ship each month. As much as I love linear tech, their support, and my personal FAE, and sales guys... I have to remember that they are trying to sell product and their product is not always best in my application. Their parts are usually high quality, highly advanced, and highly priced. But sometimes the cutting edge can lead to unknown problems and having to work extra hard to make it work properly or just having to wrap your head around how it works and why your inductor is canceled out by the closed loop of the current control - resulting in -40dB/dec loss.

The part probably works just fine. You're probably freaking out a bit about the Bode plot - I would be to. I would probably shift the zero to the left a bit to get 30 degrees or more of clearance. I'd also look at the load response and make sure the voltage response is slightly overdamped. Then test it over my temp and humidity requirements, Then I'd package it up and ship it out.