Hi,
Can anyone help me in implementation of Boolean Functions using NAND gates.
The function is D(A +B(C+A') + B' )
Thanks.

 

What would be the first step? How about a truth table or the canonical SOP form.

 

Can I do expand it and then apply DeMorgan's theorem
Something like- ( (DA + DBC) + (DBA' + DB') ) ''
((DA+BC)'. (DBA' +DB')')'
( (DA)'. (BC)'. (DBA')'. (DB')')'

Now, I can implement using NAND gates...
Is this the correct way?

 

You need to clarify what your constraints are. Are you restricted to two-input NAND gates (a very common constraint for these types of problems), or can you use n-input NAND gates?

In your work, what happened to the D in your DBC term?

 

Sorry, accidentally missed it....
The final expression would be
( ( DA)'. (DBC)'. (DBA')'. (DB')' ) '

Using three-input NAND gate, I think it can be implemented directly now...right? (Its a new course for me, I am still trying to get to the basics)
But can this be done using two-input NAND gate? How will I do it?

 

Actually, your expression reflects the use of two 2-input NAND gates, two 3-input NAND gates, and one 4-input NAND gate. And of course you also need some inverters, but those are trivial to make with a NAND gate, right?

ANY logic circuit can be implemented using nothing but 2-input NAND gates (or 2-input NOR gates, or a couple of other single 2-input logic gate options).

In this case, all you need to focus on is how to implement a 3-input NAND gate and a 4-input NAND gate using just 2-input NAND gates. To do that, consider how to make multi-input AND gates from 2-input AND gates and how to make a 2-input AND gate from 2-input NAND gates.