I have to design a BJT amplifier with the following specs

-overall swing of 8V (peak-to-peak) with rail voltages from GND to 15V
-less than 10% change in I_CQ if beta varies between 100 to 200
-overall gain of greater than or equal to 80 V/V
-DC power consumption less than or equal to 30mW

I am using the Q2N3904 BJT in a common-emitter circuit. Only transistors, capacitors, and resistors should be used in this design.

Would anyone be kind enough to help me out? How do I start designing the amplifier?

Thanks in advance!

 

Presumably this is a single stage common emitter design.

The critical condition in meeting the design specification will be the 10% limitation on collector quiescent current variation with a β range of 100 to 200.

This will require the use of voltage divider bias stabilization - probably with some emitter resistance, RE. Some important data for what follows below - the voltage divider bias circuit reduces to a Thevenin equivalent base side voltage source Vth and shunt resistance RB [RB1||RB2].

One can take two approaches in the voltage divider component choices - trail and error with some simple maths or some slightly more complex but definitive maths to get started. This revolves around deriving a relationship between the equivalent voltage divider bias resistance RB and the emitter resistance RE - given some condition on variation in quiescent Ic.

It can be shown after some effort that ...

\(\frac{I_{cmax}}{I_{cmin}}=\frac{\beta_{max}(\frac{R_B}{R_E}+(1+\beta_{min}))}{\beta_{min}(\frac{R_B}{R_E}+(1+\beta_{max}))}\)

In your case
Icmax/Icmin=1.1
βmax=200
βmin=100

Which after substitution into the above equation leads one to the requirement that

RB/RE=21.22

This is the maximum ratio of RB/RE which is allowable to ensure the Ic stability requirement is met.

You could have come up with this by repeated trial and error in the voltage divider bias design but I think understanding this condition at least is useful in reducing the overall design workload.

The value you choose for RE will depend in part on the required minimum gain of 80V/V. You can fully or partially capacitively bypass RE to obtain sufficient gain, whilst capitalizing on the DC feedback obtained through RE. These are choices the designer makes in satisfying the design goals.

At this stage I'd suggest you make a contribution to the task - since this is homework.