BJT Amp Distortion

Discussion in 'Homework Help' started by laguna92651, Mar 17, 2010.

  1. laguna92651

    Thread Starter Active Member

    Mar 29, 2008
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    I've designed this BJT amplifier. When I simulate it in pspice I get 100mv of first harmonic distortion. What values can I adjust to improve this distortion. Av, gain, needs to be between 40 and 100. Ideally I would like Vo peak to peak of greater than 6v. Rload is between 500 and 750Ω.
    Thank you
     
  2. Ghar

    Active Member

    Mar 8, 2010
    655
    72
    Can you even trust that Fourier plot?
    You have something like 10 datapoints per cycle...
    I'd set a maximum time step to make it cleaner. You set it in the simulation profile.
     
  3. Jony130

    AAC Fanatic!

    Feb 17, 2009
    3,957
    1,097
    You waveform is distort by to small "step ceiling" in your simulation.
    Set "step ceiling" 1us.
    And to improve THD use more negative feedback, add emitter follower or use more sophisticated circuit.
     
  4. laguna92651

    Thread Starter Active Member

    Mar 29, 2008
    101
    0
    Much nicer looking, thanks. What exactly does the step ceiling do?

    I've decreased the gain by increasing R10 to 10Ω. New Av=680/10 = 68 and the distortion dropped from 100mv to 32mv. Assuming the distortion measurement is accurate what is a respectible number? Are there any improvement I can make to the existing design without adding any major redesign.
     
  5. Ghar

    Active Member

    Mar 8, 2010
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    72
    The simulation calculates a result every x amount of time. It picks whatever value "works" numerically but it can skip detail.
    You can force a maximum time step to get more data points if you think it's not good enough.
     
  6. laguna92651

    Thread Starter Active Member

    Mar 29, 2008
    101
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    So in this case it is calculating a result every 1usec.
     
  7. Ghar

    Active Member

    Mar 8, 2010
    655
    72
    Every 1 usec or more often.
    The actual step depends on the signals. The simulator will start with large time steps and reduce them until it can find a result that makes sense**, then it moves on.
    You're setting the maximum (hence ceiling).

    Edit:
    **makes sense numerically. Just because it gives a plot doesn't mean it's worth anything.
     
  8. hobbyist

    Distinguished Member

    Aug 10, 2008
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    56
    Hi,

    Did you know that your load is going to reduce that gain to around 35?

    You asked if there are any improvements that can be made.

    This is not a improvement on your already well designed circuit, it looks like you have a fairly good handle on this kind of stage design, keep up the good work.

    But try and experiment with these values and see what you can get with it, on your simulator.

    RC=680
    R6=130
    Use only 1 emitter resistor.
    Bypass R6 with C6 = 2.2uf
    R2=1.3K
    R1=8.2K
    don't use R4.

    There may be some distortion, you could work out, but it may give a gain of around 40.
    With less components.
    See how your simulator works with it.

    I used my old ver. Circuit maker for this design.
     
  9. laguna92651

    Thread Starter Active Member

    Mar 29, 2008
    101
    0
    Thanks much, your suggestions are greatly appreciated, I will give them a try.
    thanks again
     
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