Hello Beenjamín

I see you use Multisim to develop your circuits.
Very good, however there are missing some connections in the circuit that you enclose.

I use Proteus ISIS. Occasionally Multisim II.

Certainly TCU(12) and TCD(13) outputs are used to achieve the goal.
And also the Inputs UP(5) and DN(4) to have the counter up or down.
Then a circuitry with a J-K Flip-Flip, in my scheme, And some gates are used to develop the circuit.
It might have been easier with a Toggle Flip-Flip type.

Note how through some OR gates are allowed to pass the 555 pulses to the counter.
If the Q of flip-flip is a low level pulses to the counter will pass right through the OR gate U3: A
and the counter will count ascending

As the Q of flip-flip is low consequently its negated Q is high thus will disable the OR gate U3: B.

Normally TCU(12) And TCD(13) outputs are at high level so that the AND gate U8: A will output a high level.

As soon as the counter reaches 9 TCU (12) will be low and the AND gate U8:A will have at its output to a low level.

This will make our Flip-Flip to change state so now have a Q high and Q negated low thus far the pulses pass right through the OR gate U3: B.

Another important thing happens with our counter.
As the gate U8:A low level generated at its output and this output is also connected to the input PL(11) of the counter, the data in their inputs D's will going to it’s Q's.
Note that these inputs D's have programmed an 8(Decimal) 1000(Binary).
D0 = 0
D1 = 0
D2 = 0
D3 = 1
So the counter will count downward from 8 to 1.

As soon reaches the counter to 1, all inputs NOR gate U5:A will have a low level so that its output will have a high level that disables the OR gate U3:C and since the 555 pulses can’t cross the right through OR gate U3:C the counter stops.

Notes:
Statute of the OR gate:
Any high level in any input will give a high level at the output. The other inputs no longer affect the output.

Statute of the AND gate:
Until all entries have high level its output will be high, so any low level in any input will give a low level at the output. The other inputs no longer affect the output.

Statute of the NOR gate:
Until all its inputs are low the output will have a high level. So any high level in any entry its output will be low. The other inputs no longer affect the output.

Take in consideration that the names of input’s and output’s differ in Multisim and Proteus ISIS. Any way the PIN numbers are the same.

Develop Your design based on mine.

regards
at your service

Using the spec of your schematic, I have built it on a breadboard. I have retraced my steps several times, but all it is doing right now is: 9-8-7-6-5-4-3-2-1 and stops. It wont count up first at all. Any ideas??

 

Hello Beenjamín

I see you use Multisim to develop your circuits.
Very good, however there are missing some connections in the circuit that you enclose.

I use Proteus ISIS. Occasionally Multisim II.

Certainly TCU(12) and TCD(13) outputs are used to achieve the goal.
And also the Inputs UP(5) and DN(4) to have the counter up or down.
Then a circuitry with a J-K Flip-Flip, in my scheme, And some gates are used to develop the circuit.
It might have been easier with a Toggle Flip-Flip type.

Note how through some OR gates are allowed to pass the 555 pulses to the counter.
If the Q of flip-flip is a low level pulses to the counter will pass right through the OR gate U3: A
and the counter will count ascending

As the Q of flip-flip is low consequently its negated Q is high thus will disable the OR gate U3: B.

Normally TCU(12) And TCD(13) outputs are at high level so that the AND gate U8: A will output a high level.

As soon as the counter reaches 9 TCU (12) will be low and the AND gate U8:A will have at its output to a low level.

This will make our Flip-Flip to change state so now have a Q high and Q negated low thus far the pulses pass right through the OR gate U3: B.

Another important thing happens with our counter.
As the gate U8:A low level generated at its output and this output is also connected to the input PL(11) of the counter, the data in their inputs D's will going to it’s Q's.
Note that these inputs D's have programmed an 8(Decimal) 1000(Binary).
D0 = 0
D1 = 0
D2 = 0
D3 = 1
So the counter will count downward from 8 to 1.

As soon reaches the counter to 1, all inputs NOR gate U5:A will have a low level so that its output will have a high level that disables the OR gate U3:C and since the 555 pulses can’t cross the right through OR gate U3:C the counter stops.

Notes:
Statute of the OR gate:
Any high level in any input will give a high level at the output. The other inputs no longer affect the output.

Statute of the AND gate:
Until all entries have high level its output will be high, so any low level in any input will give a low level at the output. The other inputs no longer affect the output.

Statute of the NOR gate:
Until all its inputs are low the output will have a high level. So any high level in any entry its output will be low. The other inputs no longer affect the output.

Take in consideration that the names of input’s and output’s differ in Multisim and Proteus ISIS. Any way the PIN numbers are the same.

Develop Your design based on mine.

regards
at your service

This what I have and what I have built. But it is only counting down then stopping, it isn't counting up first let alone counting up at all.