hi,
im doin a project where i need to convert binary to ami using a xilinx spartan 3-200 and im a bit stuck,
basically i will program a screen to pop up using c++ and the user will input a 48bit binary sequence which will be transferred to the board (rs232)and output over the dac and displayed on an oscilloscope as its ami encoded equivalent,

i reckon i will have to design some sort of state machine that will be asynchronous or is ther an easier way? i will be using the schematic editor to simulate the logic.

does the binary have to be converted to hex before being transferred to the fpga?

is there any good sites that can help me design a glitch free encoder ie state machine tutorials? or maybe ye are able to provide all the answers i need!

in any case any help would be greatly appreciated.

 

1. RS-232 mark and space levels for logic high and low have no relation whatever to AMI encoding. I'm impressed by your 48 bit DAC, could you post up it's spec sheet?

2. What is the requirement that would make asynch superior to synchronous?

3. No. Think about hexidecimal for just a moment.

4. Glitch-free implies mechanical-to-logic transitions. Look up "excess-3 gray coding" for a start. De-glitching mechanical inputs is pretty easy. There's even logic IC's like the 74LS279 and the CD4044 made to do that.

 

i think maybe partially misunderstood my question.

The project is to get us using the xilinx ise 9.2 software to program a spartan 3 fpga that is mounted on an educational board with 7seg displays and switches and a DAC and an ADC. im not sure what resolution the dac is, the board is from digilent and its a nexys board. anyway, the project will consist of typing in a random array of 1's and 0's when prompted. this will then be transfered serially to the nexys board in which case the programmed board will convert the binary to RZ-AMI and output through the DAC serially to be displayed on an oscilloscope.
i will be using the schematic editor in the xilinx ise program to arrange my logic for the io block and a ucf file to wire this to the fpga.
as there is a 64 bit bus available within the board i will be using 48 bits with a redundancy of 16 for some ecc or parity if time permits.
as for being asynchronous im not so sure why i thought this would be better, any suggestions? whats normal?
the ami code will have to be output to the scope at a low enough frequency to be able to clearly see the mark inversions etc.

once this part is implemented i have to alter this to o/p hdb3.

 

Noughty noughty trying to get some one else to do your problems !! could always ask sean he can probably solve it faster then any 1 here