I am currently working on a project that involves the use of binary counters. This is my first time using them so I am a little bit confused about certain enable pins on a binary counter.

The IC I am using is the 74F269 from NXP.
http://www.nxp.com/documents/data_sheet/74F269.pdf

I am just wondering what do the CET, CEP and PE pins do. I could not find any useful information on the datasheet or google.

 

CET and CEP are used for cascading the counters as shown in Figure 4 in the data sheet. PE is to parallel load (jam) the counter with a desired count value (the Px inputs), for example if you wanted to count down from a known input (programmable count).

A short description of the pin functions is shown in Table 2 (did you miss that?).

 

PE allows the data bits to be loaded in parallel into the counter.
The 'Functional Description' and Figs 1 and 2 of this datasheet explain how CET and
CEP are used:
http://www.google.co.uk/url?sa=t&rc...hU6M6JuEt7_cabw&bvm=bv.62922401,d.bGQ&cad=rja