Now I understand what you were meaning...
Yes you are right you have to use a 0-15 counter.

One thing that I'm not understanding is how the counting passes to 10000b when there's no possible way to the 2nd clock change because the timer counts only to 9 and so the output of the AND gate is never 1...

EDIT: forget this last phrase... I see now that you change the counter to a 4520. Sorry, my mistake...

 

OK, it all depends on how you want it displayed. Either you weren't very clear on that, or I just didn't read it correctly.

I thought you wanted it displayed as HH MM SS, four LEDs for each digit that would count 0-2, 0-6, or 0-9 depending upon their display function - in other words, BCD. In that case, the 4518 would be the ticket. But for a modified binary display, the 4020 is what you need.

Have at it!

 

Right it must have been a misunderstanding on my part. I did not mean 4 leds per digit, I meant 6 for both digits, sorry. Thanks for the clarification!

 

Now if you want a clock that's more challenging to read - build a 24-hour purely binary clock

It's brutal to read initially, but you'll soon learn to translate from decimal/hex/binary and back again in the blink of an eye, and very few of your friends will have a clue how you know what the time is

 

SgtWookie: your idea is very cool I think I'll do it my self, specially the part:

...and very few of your friends will have a clue...

 

By pure binary what do you mean? 1 set of led's for every digit?

 

Ok I have added the 1hz from mains circuit and an auto dimmer. Does anyone see any problems with it? The logic should be right it tested it in the simulator and it goes from 0-59 so it should work.

its pretty big!

 

Looking much neater than last iteration

The first glaring omission: current limiting resistors on the bases of the 2N2222 transistors! Without them, the outputs of your CMOS IC's will not be able to rise above about 0.7V, and the logic attached won't function properly.

A very quick check of an Intersil datasheet for a 4520 indicates with a Vdd of 5V, an output can source up to 0.53mA @4.6V. You better use less than half of that.

Were the 2N2222 transistors MOSFETs or IGBTs, you would not have to worry about base current.

You should check the hFE on the transistors you're planning on using. I just checked a dozen or so 2N2222 and MPS2222A's I have kicking around here. Worst case was 182, best was 245, average was around 210, MPS2222A's were mostly 190. "Your Mileage May Vary - Considerably!" Buy extra 2N2222s, you can use the extras for another project down the road.

As you test your transistors for hFE using a DMM with hFE function (they're frequently on sale at places like Harbor Freight for under $5) stick a label on each transistor with a number, and note the reading in a spreadsheet. Select the group of transistors that has the closest hFE rating. Otherwise, your LEDs will have different intensities.

For now, let's figure that you'll get a group of transistors with an hFE of at least 180. For each unit of current you put in the base, you should get 180 units out (up to saturation, of course.)

So, if you need at least 30mA of current sinking, you will need to put in 0.167 mA of current. By George, I think we can do this

So, let's see - let's go for overkill. We'll dump 0.2mA into the base. That'll leave us with 0.33mA of current, so we're still within limits. So how do we figure the resistor?
The base voltage will normally be at somewhere around 0.63V. According to the datasheet, 0.53mA source when Vdd=5
So, 5v -0.63v = 4.37V
R = E / I
R = 4.37V / 0.2mA
R = 4.37 / 0.0002
R = 21850
So use a 22k resistor to limit the current on each transistor's base, as that's the closest standard value.

The next problem ... is the implementation of the dimming phototransistor.
You have 17 LEDs, of which none to most of which may be lit, and nothing to limit the current but the phototransistor! I'm afraid that this will not work very well.

However, it's late and this must be returned to later.

 

Why does U3 Vdd go to a counter output (note that both sides of J2 go to the same point)?

U5-38 will never see a low, J1 can only supply a high and same for AND6 thru D1.

The clock at U14 shouldn't be driven directly by the 120Hz ripple, the slope is too slow and can cause poor clocking and thus miscounts. Run it into a Schmitt trigger to create the clock drive.

There is no smoothing cap into or out of the regulator? Add a 470 ohm between the reg out and ground, this will draw 10mA for regulator stability.

 

Yeah, looks like LED1 got accidentally connected to both the dimming phototransistor and the clock line from U15; that simply won't do.

After that, the Vcc needs to be straightened out; separated from the clocking line. You don't want to dim the Vcc, either.

You need to do something with every pin 13 on the 4017s, and the -1CLK. and -2CLK on the 4520 inputs. You must never leave a CMOS input floating, or you will have problems.

 

Thanks for your great criticizing! but thats what I need so thanks!

Ill get to work with your suggestions and ill look for something else to do the dimming.
Thanks for your help!!

 

Thanks for your great criticizing! but thats what I need so thanks!

Ill get to work with your suggestions and ill look for something else to do the dimming.
Thanks for your help!!

*EDIT* ok I fix some of what you said.
heres a new circuit. Im look for a dimmer circuit atm.

 

You must've trimmed off the "Node 9" identifier. If you look at LED12, up and to the right of it, there is a break in the wire.

You are not being consistent in your use of junctions (the dots where wires join). They MUST be used where three or more wires meet. In places where just two wires meet, or a wire meets a component, you should either place a junction at ALL such connections, or leave it understood that the wires are connected at that point, and place NO junctions unless there are three or more wires coming together.

You have not yet fixed the floating inputs. Everything on the left side of your ICs needs to be connected to something; a signal, Vss or Vdd.

Your "Keys" - right now, by pressing a key, you short a clock signal to Vss. This is not a good thing.

Instead, consider using a SPDT switch, with the CLK input on the common.

One way (NC) the common is connected to the normal clock.

The other way (NO) the common gets connected to the divide-by-10 output from U14.

This way, you won't have to sit there frantically mashing the "set" button to manually generate clock pulses. Besides, you're going to need a de-bounce routine.

 

Sorry about the junctions ill try to clean that up.

I don't get what you mean by "SPST switch, with the CLK input on the common."
What common on the switch?
Do you mean a SPDT?

 

Yes, I did indeed mean SPDT switch. Sorry for the confusion.

 

1) The CLK inputs for U3/U5/U9 are not going to work, they have no reference to pull them low. Place a 1K to GND on each of these.

2) The output of U15 (+15V) is probably going to blow out U3 (+5V).

3) Although I think I understand why you're using devices at +15V, it is not a good design practice. You should use 5V logic devices of the same family, and adjust the 120Hz ripple input to U17A for respective logic compatibility.

4) Also, it's not good to run an unfiltered voltage directly into the U16 regulator. You should devise a way to filter the U16 input with 470uF - 1000uF, and still manifest the bridge-diode ripple (120Hz) as a clock source by adding circuitry and tapping off somewhere else per item 3 above.

 

This belongs below nomurphy's reply; the re-setting of the board's clock caused this reply to post earlier than it should have.

1) The CLK inputs for U3/U5/U9 are not going to work, they have no reference to pull them low. Place a 1K to GND on each of these.

This was addressed by my prior comment of "floating inputs"

2) The output of U15 (+15V) is probably going to blow out U3 (+5V).

U15, as well as all of the other ICs, are powered by 5VDC. I believe the _15V suffix for the part number is in his schematic capture program's IC library, and he can't remove it without removing the link to the model.

3) Although I think I understand why you're using devices at +15V, it is not a good design practice. You should use 5V logic devices of the same family

They are all 4000-series CMOS, and have the typical operating range of that family.

, and adjust the 120Hz ripple input to U17A for respective logic compatibility.

This is a good point; he still hasn't corrected that part of the supply. The input to U17A should be from a diode connected to the transformer's output prior to the rectifier bridge, with a series current limiting resistor of around 10K.

4) Also, it's not good to run an unfiltered voltage directly into the U16 regulator. You should devise a way to filter the U16 input with 470uF - 1000uF, and still manifest the bridge-diode ripple (120Hz) as a clock source by adding circuitry and tapping off somewhere else per item 3 above.

Good points.
C1 is only 10nF; vastly undersized.
There should also be two caps on the output of U16, one 0.1uF ceramic or tantalum, and an electrolytic of about 10uF.

 

Ok I did the changes you recommended. Also I removed the diode bridge, was that fine?

 

Try it as in the attached:

 

The diode bridge actually needs to be in there to rectify the AC output of the transformer to DC.

See attached.
The phototransistor you have hooked up won't work as you expect it to, because the collector current is blocked by the capacitor. Where did you find that portion of the circuit?