biasing MOS over a drain-gate resistance

Discussion in 'Homework Help' started by Starhowl, Dec 4, 2013.

  1. Starhowl

    Thread Starter New Member

    Dec 3, 2013
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    I do understand the equations behind biasing a MOS over a drain-gate resistance, but why is this resistance usually in the MOhm range?

    As there is no current flowing into the gate would it not matter how big or small the resistance is? As Vgs = Vds in this case for every resistance is valid?
     
    Last edited: Dec 4, 2013
  2. WBahn

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    Mar 31, 2012
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    Could you please provide a schematic for the circuit you have in mind?
     
  3. LvW

    Active Member

    Jun 13, 2013
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    Are you sure that you ask for the DRAIN-gate resistor (rather than gate-source resistor)?
     
  4. WBahn

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    I've never heard the phrase "biasing over a xxxxx resistor", so I, at least, really need to see a sketch.
     
  5. Starhowl

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    Dec 3, 2013
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    I attached a schematic to your convenience to my original post.

    The corner frequency can be estimated by taking the sum of the 2 time constants and then taking their inverse. But if R_G is high, the time constants get maxed out thus lowering the corner frequency, an unwanted effect.

    Yet it usually would be in the MOhm range?
     
  6. Papabravo

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    Feb 24, 2006
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    When there is no current flow there is no potential difference. An MOS transistor with a floating gate is like having a tiger by the tail. Vg can be anything and the resulting chaos would be hard to tame or even characterize. What you want is a situation where in the absence of any signal input the transistor is in a known and defined state. The resistance can be large because very little DC current can flow into or out of the gate. The value is not critical for establishing a quiescent condition. In operation you want this biasing resistance to be large so only a tiny fraction of the signal current is diverted from the gate to the drain(source).
     
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  7. Starhowl

    Thread Starter New Member

    Dec 3, 2013
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    The current is exactly 0 no matter what value R_G has; it was not about a floating gate potential or why the resistance is attached to the gate, but why it usually would be in the MOhn range; in addition I now also found out it worsens the amplification in high frequency range.

    But uhm... Yeah you're right.. It's about the signal not being diverted from gate to drain! Too bad it worsens high freq. though.. Thank you for your thoughts!
     
  8. WBahn

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    Without a signal, you have what is essentially a diode-connected FET. A true diode-connected FET would have a direct connection between drain and gate.

    But with a diode-connected FET, the input signal is directly coupled not only to the gate, but to the drain as well, which is undesireable. The presence of the gate resistor reduces the coupling. The bigger it is, the less the coupling.

    Everything's a compromise.
     
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  9. WBahn

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    The DC current is zero, but the AC current is not. Remember, the gate is a capacitor to the drain, source, and channel. Current has to flow onto it and off of it in order to change the gate-source voltage. Current flow to the gates are the dominant power dissipation mode in CMOS circuits.
     
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  10. Papabravo

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    Feb 24, 2006
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    And I wrote my response without seeing your sketch so now you know why it is important because sometimes words lack the ability to convey certain critical pieces of information.

    @WBahn -- right you are!
     
  11. LvW

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    Jun 13, 2013
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    OK - now I know what you mean.
    * At first, let me answer in a - more or less - general way:
    There is something like a "natural" law in electronics:
    When you are going to redesign a circuit in order to improve one specific property you can be sure that - at the same time - another circuit property will become poorer.
    * Now, to your problem: It is a well-known fact that a small input resistance in conjunction with the input capacitance gives a small time constant - however, as you can imagine there are certain lower limits for the operational input resistance (loading of the signal source).
    * Thus - following the above mentioned general rule, you always have to find a trade-off between both conflicting effects: Large input resistance is good - however, you have to pay with a larger time constant (lower cut-off frequency). In principle, such an effect cannot be avoided - perhaps using some advanced circuit techniques (bootstrapping, second stage,..?). However, in this case, you have to pay with an increased parts amount.

    * EDIT: In this context, I remind you on the 50 ohms principle for high frequency circuits.
     
    Last edited: Dec 4, 2013
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