Hi, I am trying to bias the following schematic. It appears to be working, but the o/p sine wave (green) @ C2 R3 junction kinda looks odd and fat at the top side. Blue one is the i/p signal wave.
Another thing is, in many class A schematics, I find they put large value caps @ C3, but when I do so with 10uf, o/p signal really messes up.
Looking for any explanation / workaround / suggestion regarding the above, thanks.
Another thing is, in many class A schematics, I find they put large value caps @ C3, but when I do so with 10uf, o/p signal really messes up.
Looking for any explanation / workaround / suggestion regarding the above, thanks.