Bi-Polar Op Amp

Discussion in 'Homework Help' started by laguna92651, Mar 31, 2010.

  1. laguna92651

    Thread Starter Active Member

    Mar 29, 2008
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    I've design the attached bi-polar op amp.
    Required Specs:
    400<=Ad<=500
    Rid >= 20KΩ
    fL3db <=100Hz
    Voffset <=.01v
    Ro <=200Ω
    Vop-p>=2v
    RL=200Ω
    PS=+and - 10v

    (The beta for the 2N2222 in my pspice model is 255)
    I've inputed a 5mv peak to peak signal and get 2.47 v out p-p which is a gain of 494, which meets spec. The gain of each stage does not match what I calculate they should be.

    Adiffcalc=71
    Adiffpspice=34

    Againcalc=36
    Againpspice=15.9

    Atotcalc=2597
    Atotspice=594

    What formulas should I use to calculated the stage gains.

    Second question, I picked R12 to be 680Ω so I would have 15mA collector current, I calculate Rout to be 1.7Ω, is this correct and is it a reasonable value?

    I had asked a similar question a few weeks ago and didn't really understand the answer. How do I calculate the maximum peal to peak output voltage that this circuit can generate. I then assume the maximum input voltage would just be the max output divided by the gain?
    Thanks for your help.
     
    Last edited: Mar 31, 2010
  2. Jony130

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    Feb 17, 2009
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    But where is the schismatics?
     
  3. laguna92651

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    Mar 29, 2008
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    oops!
    I think I have the gain issue taken care of, but any inputs greatly appreciated. My main issue is how to calculate the maximum peak to peak output and max input.
    Thanks
     
  4. t_n_k

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    Mar 6, 2009
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    Hello laguna92651,

    How did you arrive at a calculated differential stage gain of 71?

    This doesn't make much sense to me.

    The differential stage gain would be a maximum of 1500/66=22.7

    I roughly calculate the differential stage gain as ~21.1 and the amplifier stage mid-band gain as ~23.6, giving an overall gain of ~498. This is pretty close to your simulated (?) gain of 494.

    Maybe you should provide some details of how you arrived at your calculated values.
     
  5. laguna92651

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    Mar 29, 2008
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    These are the equations I used, I left out the Re for Ad1 in the original post and I changed beta to 100, I now get 17.0 for Ad1 and 37.5 for A2.

    Ad1=gm(Rc||Ri2)/(2(1+gm*Re))
    A2=(IR4/2VT)(R5||Ri3)
    A3=(1+B)*(R12||ro)/(rpie6+(1+B)*(R12||ro))

    For Ad1 you used 1500/66, which I assume is Rc2/(2*R11)? If, so why did you use 2*R11 instead of just R11?

    How did you get 23.6 for the gain stage, if I didn't use the more involved equation I would have used R8/Re4A=390/11=35.4.

    Do you have a rule of thumb for the common emitter gain?

    I still need to calculate the max output peak to peak signal and max input peak to peak.

    Thanks for your help.
     
    Last edited: Apr 3, 2010
  6. PRS

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    Aug 24, 2008
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    Why do you go through a 1.3 k resister before the signal goes to the output transistor?
     
  7. laguna92651

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    Mar 29, 2008
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    Q5 and Re5, 1.3k, are to adjust the dc level of Vo to 0v for 0 input. Any thoughts on how to calculate the max output swing peak to peak and max input peak to peak?
     
  8. t_n_k

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    I believe the differential stage gain is |Av|=Rc/[2(RE+re)] (I assumed β is large and matched for each transistor). 're' is the dynamic emitter resistance.

    For the second stage I used |Av|=Rc/(RE+re)

    In either case 're' is dependent on the steady state emitter current(s). I use re=26/IE(mA)
     
  9. laguna92651

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    Mar 29, 2008
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    What do you use to calculate the maximum peal to peak output voltage and max input peak to peak?

    What do you use to calculate the common emitter gain?
    Thanks
     
  10. t_n_k

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    I've rechecked my rough calculations and revised the predicted gains for each stage.

    The diff amp pair have a total emitter current of 5.35mA - per your schematic.

    So each transistor has static emitter current of 2.68mA. So re for each transistor is 26/2.68=9.7Ω.

    So the diff amp gain would be around 1500/[2*(33+9.7)]=17.6 (not 21.1 as I originally predicted)

    The second stage gain would be 390/(11+re). In this case re=26/4.7=5.53Ω

    So 2nd stage gain would be 390/16.53=23.6 (as I found previously)

    This would give an overall gain of around 415.

    In reality, these numbers probably will be optimistic - I haven't taken into account the loading effect on the stage gains. I'm not sure to what degree the Darlington configuration will load the the diff amp output - notionally the effective load into the Darlington base will be high but there may be feedback degradation. Nor am I sure of the effective load seen at the second stage output - the effective collector load is probably something lower than 390Ω. So the overall gain may be substantially lower than the 415 value.

    It's a lot of work doing a complete analysis. Maybe someone else is willing to go the extra mile.
     
  11. t_n_k

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    On reflection - A better estimate for the Darlington amplifier stage gain is probably....

    |Av|=390/(RE+2re)=390/(11+11.1)=17.7

    This would give an overall Av of 17.6*17.7=312 which is considerably less than the 415 value I quoted earlier.

    In fact your simulation should show a gain commensurate with the revised estimate of Av=~300
     
    Last edited: Apr 4, 2010
  12. Jony130

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    To find max output negative voltage we need to find Vo in this circuit :

    [​IMG]
    So max output negative voltage is equal:
    -V_max = RL/(RL+R12)* Vee = - 2.5V


    To find max positive output voltage we need to find Vo for this circuit:

    [​IMG]


    So you need to use DC analysis to find Vo. And if you find Vo then you will know +V_max.
    And if we do this by inspection we get:
    10V - 0.7V - 5.4mA*1.3K - 0.7V = 1.6V
    So you design terrible amplifier, which wasted a lot of power supply voltages.
     
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    Last edited: Apr 4, 2010
  13. laguna92651

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    Mar 29, 2008
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    What I ended up doing was finding the ac load line, by getting the Thevenin eq circuit of the output stage.

    Δ ic = 2*Icq = 2*(12.5m) = 25ma
    vce = Δic6*(R12||RL)
    R12||RL = 680||200 = 154Ω
    vce = 25m*(154)
    vce = 3.8 vo p-p

    I assume Vi max = vo p-p/Atot? (should I check what vin does to the diff amp)
    What is a rule of thumb for the gain of the common emitter?
    Could you explain what you did to find +V_max? Why did you use Q5?
    Thanks for the help.
     
  14. Jony130

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    Yes Vi_max=Vo_pp / Atot


    Au = Rc||RL/ (re +Re) but you use Darlington so you have two re.
    So you get 390/(RE+2re)

    The max positive voltage swing of a common emitter we get when BJT is cut-off.
    So if Q3, Q4 is cut off we end-up only with Q5 and Q6
     
  15. laguna92651

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    Mar 29, 2008
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    Quote:
    What is a rule of thumb for the gain of the common emitter?
    Au = Rc||RL/ (re +Re) but you use Darlington so you have two re.
    So you get 390/(RE+2re)

    I think you are referring to the Darlington stage I was asking about the final out stage gain, of the emitter follower, it was my fault when I asked the question to begin with, it should not have been common emitter.
    Hope you had a nice Easter.
     
  16. Jony130

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    Last edited: Apr 5, 2010
  17. t_n_k

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    That's correct ... I was considering the Darlington stage. I now realise you wanted gain for the somewhat complex emitter follower stages.

    Well, if you were considering the gain from Q3 collector (or Q5 base) to the output I would have (assuming equal β values for Q5 & Q6)

    Av=\frac{(RL||(R12+re6))}{(RL||(R12+re6))+\frac{(Re5+re5)}{(1+\beta)}}

    which I calculate would give Av=0.97 for β=250 and the values shown on your schematic.
     
  18. laguna92651

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    Mar 29, 2008
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    Jony130 and tnk thanks very much for your help. Attached is an output plot and I noticed that the lower half of the sine wave is narrower than the upper portion, width of 479us vs. 384us. What portion of the design causes this non-symmetry of the sine wave.
     
  19. t_n_k

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    Possibly the Darlington stage - try replacing the 2N2222 pair with a single higher β type. The overall gain may be lower but the distortion may be reduced. Let us know if that turns out to be the problem and then you/we might be able able to come up with an explanation of the mechanism.
     
  20. laguna92651

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    Mar 29, 2008
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    Going with 1 transistor seemed to produce no distortion, visually. If I measure it with the pspice cursors there is a slight difference, approx 20us, but that could easily be operator error. Attached is my current configuration, I changed the Iref and IQ. The original design had the same problem.
     
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