Is there a systematic way in which l can determine the behavior of this sequential circuit ?

 

look at the T-flip flop on this page http://en.wikipedia.org/wiki/Flip-flop_(electronics)

 

Yes, the way is "patience". Start the Flip Flops from the 0 state, and record how they change with every clock cycle. It should take 8 clock cycles to go through all possible permutations (a full period of the output signal).

 

But how l draw T on the timing diagram ? I tried that and it didn't work

 

As we always say in the HW forum, be specific and post your work, no matter how wrong it is. This is the way to get good help.

You didn't mention before a timing diagram. Is this what you want or simply the sequence of the output?

 

I have the exact same question on my assignment. We must both share the same terrible professor.

I've given an attempt at drawing the timing diagrams, they are attached to this post.

I'm not 100% if this is right, or if it has enough clock pulses to completely describe the behaviour of our sequential circuit, but hopefully (if it's right) it will give you a better idea of what to do.

I suggest having the T flip flop excitation table handy while drawing the timing diagram if you aren't comfrotable with them yet.

 

Jegues, I 'm afraid you didn't quite get it.

You see, there is a small time frame before the output of the first FF is updated with the input. At that time frame, the HIGH signal hasn't yet reached the input of the second FF but the clock positive front has expired. Consequently the second FF won't be updated simulatneously with the first.

Check the image for a general picture. Don't bother about the amplitudes, I have offset them anyway. From up to down we have the clock and the 3 FFs.

Sure enough, it took 8 cycles to make a full period.

 

Jegues, I 'm afraid you didn't quite get it.

You see, there is a small time frame before the output of the first FF is updated with the input. At that time frame, the HIGH signal hasn't yet reached the input of the second FF but the clock positive front has expired. Consequently the second FF won't be updated simulatneously with the first.

Check the image for a general picture. Don't bother about the amplitudes, I have offset them anyway. From up to down we have the clock and the 3 FFs.

Sure enough, it took 8 cycles to make a full period.

I think my signals for Q0, and Q1 correspond with your answer, just not Q2.

Is this correct?

 

Nor Q1 or Q2 correspond to my answer. I should have pointed it out more, but Q0 starts rising at time 0, the same time the first clock pulse comes.
Both Q1 and Q2 stay at LOW at time 0+.

 

Nor Q1 or Q2 correspond to my answer. I should have pointed it out more, but Q0 starts rising at time 0, the same time the first clock pulse comes.
Both Q1 and Q2 stay at LOW at time 0+.

Yes but on my figure I did not start with a HIGH clock pulse, I started with a LOW clock pulse.

Do I have to start with a HIGH clock pulse? Why can't I start with a LOW clock pulse?

EDIT: Whoops, I see what you're saying now. So what happens if I start my clock at low, it will pass one pulse with no change in Q0 and Q1, and then follow your pattern?

 

I am trying to understand how you got the timing diagram for Q2 or what is labelled as Channel D in your picture.

 

I have the exact same question on my assignment. We must both share the same terrible professor.

I've given an attempt at drawing the timing diagrams, they are attached to this post.

I'm not 100% if this is right, or if it has enough clock pulses to completely describe the behaviour of our sequential circuit, but hopefully (if it's right) it will give you a better idea of what to do.

I suggest having the T flip flop excitation table handy while drawing the timing diagram if you aren't comfrotable with them yet.

Which varsity are you at ?

 

A duration of \(T_{\tiny{LOW}}\) to be exact.

And, yes, Q0, Q1 and Q2 will wait at LOW until the first clock pulse starts the sequence.

 

A duration of \(T_{\tiny{LOW}}\) to be exact.

And, yes, Q0, Q1 and Q2 will wait at LOW until the first clock pulse starts the sequence.

As far as the delay between the flip flops would this be correct:

-Q0 will activate on the first positive edge of the clock.

-Q1 will activate on the second positive edge of the clock.

-Q2 will activate on the third positive edge of the clock.

I was finally able to get the same timing diagram as Georacer.

So the counting sequence according to Georacers diagram would be:

100, 010, 111, 000 and then it will repeat.

The solution lists it as 000, 100, 010, 111, 000. Is it safe to assume that the "solution" started its timing diagram with the clock pulse low as opposed to high?

This would explain why the 000 bit is at the end for us, and not at the front.

Would we be incorrect if we said that counting sequence was infact:

100, 010, 111, 000?

Because it's going to depend on how the state of clock pulse when you started your timing diagram, correct?

 

It would be more correct to say that Q1 is activated on the first positive edge after Q0 rises and stays to HIGH. Same for Q2 and Q1.

The sequense does circles continuously. There is no differense if you say that the numbers are 100, 010, 111, 000 or 111, 000, 100, 010.

We assumed a LOW pulse too, but as a steady state, much like if it happened on minus time. We place a positive edge on time 0, not a HIGH level. But all this is rather unnecessary, as no matter when or how we start giving the pulses, the circuit will begin "countin" on the first positive edge it gets.