beginner with vhdl -- problem with S/P conv

Discussion in 'Embedded Systems and Microcontrollers' started by Ahmed Adel, Sep 19, 2009.

  1. Ahmed Adel

    Thread Starter Member

    May 12, 2008
    18
    0
    hi guyes ..
    i am new to vhdl and i tried to write code for serial to parallel converter but it doesn't perform well .. that is the code but b4 u read it, let me explain my idea so that you get the idea quickly ..

    it is 4 bit S/P .. i used DeMUX with selection bits incremented each clock so that each input bit is stored in the signal called s. after the selection reaches "11" meaning the 4 bits have been completely appeared on the signal s, then i let the output pins (dout) carry the content of the signal s ..

    please if anybody can help fix the bug in my code ..

    by the way, i am using FPGAdvantage by Mentor Grphx ..

    thx in advance ..

    Code ( (Unknown Language)):
    1. --
    2. -- VHDL Architecture AHMED_lib.Parallel_Serial_DeMUX.Behave
    3. --
    4. -- Created:
    5. --          by - Ahmed.UNKNOWN (AHMED-PC)
    6. --          at - 22:04:50 09/17/2009
    7. --
    8. -- using Mentor Graphics HDL Designer(TM) 2005.3 (Build 75)
    9. --
    10. LIBRARY ieee;
    11. USE ieee.std_logic_1164.all;
    12. USE ieee.std_logic_arith.all;
    13. USE ieee.std_logic_unsigned.all;
    14.  
    15. ENTITY Parallel_Serial_DeMUX IS
    16.   port (din: in std_logic;
    17.         dout: out std_logic_vector (3 downto 0);
    18.         clk,rst: in std_logic);
    19. END ENTITY Parallel_Serial_DeMUX;
    20.  
    21. --
    22. ARCHITECTURE Behave OF Parallel_Serial_DeMUX IS
    23. signal s: std_logic_vector (3 downto 0):="0000";
    24. signal sel: std_logic_vector (1 downto 0):="00";
    25. BEGIN
    26.   process (clk,rst)
    27.     begin
    28.       if clk'event and clk='1' then
    29.         if rst='0' then
    30.           s(conv_integer(sel))<=din;
    31.          
    32.             CASE sel is
    33.               WHEN "11" =>
    34.                 dout<=s;
    35.                 dout(3)<=s(3);
    36.                 sel <="00";
    37.                 s<="0000";
    38.               WHEN others =>
    39.                 sel<=sel+"01";
    40.             END CASE;
    41.            else
    42.           dout<="0000";
    43.           s<="0000";  
    44.       end if;
    45.   end if;
    46.     end process;
    47. END ARCHITECTURE Behave;
     
  2. scythe

    Active Member

    Mar 23, 2009
    49
    5
    Hey Ahmed, it looks to me like you are trying to do too much in your process statement. I don't know if your errors are in simulation or synthesis, but I'm willing to bet that synthesis isn't working (it's not downloading to the board correctly).

    What I suggest you do is have the clock and synchronous reset in a process by themselves and then have another process for your sel signal switch statement.

    Also, you have forgotten sel from your parameter list.

    One of the things I've noticed about VHDL is that you can have simulatable code that WILL NOT synthesize. This can happen if you have complex process blocks. It is better to break it up so that you have a lot of processes that are simple. Usually this can make your code synthesizable.

    Hope this helps for what it's worth. Good luck.
     
  3. Ahmed Adel

    Thread Starter Member

    May 12, 2008
    18
    0
    hi scythe ..
    i don't have board but i am working in coding only .. there is no error appear to me but the system doesn't function as i want .. the bug is that the signal 's' gives the desired output but the pins 'dout' don't although the statement;
    Code ( (Unknown Language)):
    1. dout <=s;
    as if the compiler ignores this statement ..

    i will try to break up my design into many processes and will follow up ..

    thanks alot man .. very nice spirit here in this board ..:D
     
  4. Ahmed Adel

    Thread Starter Member

    May 12, 2008
    18
    0
    haaaaaaaaaaaaaay yeah yesssssss ... i found it ..

    very strange solution do u know ..?? they are variables instead of signals ..

    but does anybody know why was this the bug .. ??????
     
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