Beginner Problem in VHDL

Discussion in 'Embedded Systems and Microcontrollers' started by MDS, Nov 19, 2009.

  1. MDS

    Thread Starter New Member

    Nov 19, 2009
    1
    0
    Hello Everybody,
    I'm a beginner in VHDL and I hope you can help me.I have 3 files.Testbench of a 16bit counter and a clkAndReset generator and a 16 bit counter. I have to use the generated clock and reset in the clkAndReset file in counter but I don't know how to do this.
    Here are my three files :

    Testbench :
    Code ( (Unknown Language)):
    1. [COLOR=Black]library ieee;
    2. use ieee.std_logic_1164.all;
    3.  
    4. entity testbench_synchroner_zaehler is
    5.   --leer
    6. end testbench_synchroner_zaehler;
    7.  
    8. architecture bhv of testbench_synchroner_zaehler is
    9. component clkAndReset is
    10.      generic (T : time := 20 ns);
    11.      port (
    12.        -- TAKT SIGNAL
    13.        clk     : out std_logic;
    14.        -- RESET SIGNAL
    15.        reset   : out std_logic;
    16.        
    17.        SIM_end : in std_logic
    18.        );
    19.    end component;
    20.    
    21.    component zaehler is
    22. port (
    23.   clk_Z : in std_logic;
    24.   reset_Z : in std_logic;
    25.   Q_Z : OUT std_logic_vector(15 downto 0));
    26. end component;
    27.    
    28.    signal clk1 : std_logic;
    29.    signal reset1 : std_logic;
    30.    signal sim_end1 : std_logic;
    31.    signal Q1 : std_logic_vector(15 downto 0);
    32.    
    33.    begin
    34.        reset1<='0';
    35.        sim_end1<='0';      
    36.        
    37.       u2 : zaehler port map(clk1,reset1,q1);
    38.       u1 : clkAndReset port map(clk1,reset1,sim_end1);
    39.     end bhv;
    40. [/COLOR]
    ClkAndReset:
    Code ( (Unknown Language)):
    1.  
    2. library ieee;
    3. use ieee.std_logic_1164.all;
    4.  
    5. -- ----------------------------------------------------------------------------
    6. -- entity                                                                    --
    7. -- ----------------------------------------------------------------------------
    8. entity clkAndReset is
    9.   generic (T : time := 20 ns);
    10.   port (
    11.     -- TAKT SIGNAL
    12.     clk     : out std_logic;
    13.     -- RESET SIGNAL
    14.     reset   : out std_logic;
    15.    
    16.     SIM_end : in std_logic
    17.     );
    18. end clkAndReset;
    19.  
    20. -- ----------------------------------------------------------------------------
    21. -- architecture                                                              --
    22. -- ----------------------------------------------------------------------------
    23. architecture clk of clkAndReset is
    24.   signal counter: integer:=0;
    25.   begin
    26.       process
    27.           begin
    28.               if SIM_end = '1' then
    29.                   clk <= '0';
    30.                   wait;
    31.             else
    32.                counter<=counter+1;
    33.                clk<='0';
    34.                wait for T/2;
    35.                clk<='1';
    36.                wait for T/2;
    37.                if counter>4 then
    38.                    reset<='1';
    39.                    else
    40.                    reset<='0';
    41.             end if;
    42.            end if;
    43.        end process;
    44. end architecture;
    45.  
    Counter :
    Code ( (Unknown Language)):
    1.  
    2. [COLOR=Black]library ieee;
    3. use ieee.std_logic_1164.all;
    4. use ieee.std_logic_arith.all;
    5. use ieee.std_logic_unsigned.all;
    6. use ieee.std_logic_arith.all;
    7.  
    8. entity zaehler is
    9. port (
    10.   clk_z : in std_logic;
    11.   reset_z : in std_logic;
    12.   --SIM_end : in std_logic;
    13.   Q_z : OUT std_logic_vector(15 downto 0));
    14. end zaehler;
    15.  
    16. architecture behavior of zaehler is
    17.  
    18.   signal clk1 : std_logic;
    19.   signal reset1 : std_logic;
    20.   signal counter:std_logic_vector(15 downto 0);
    21.  
    22.   begin
    23.       process
    24.         begin
    25.           if reset_z = '1' then
    26.           counter<="0000000000000000";
    27.           Q_z <= counter;
    28.         end if;
    29.         if (clk_zlibrary ieee;
    30. use ieee.std_logic_1164.all;
    31. use ieee.std_logic_arith.all;
    32. use ieee.std_logic_unsigned.all;
    33. use ieee.std_logic_arith.all;
    34.  
    35. entity zaehler is
    36. port (
    37.   clk_z : in std_logic;
    38.   reset_z : in std_logic;
    39.   --SIM_end : in std_logic;
    40.   Q_z : OUT std_logic_vector(15 downto 0));
    41. end zaehler;
    42.  
    43. architecture behavior of zaehler is
    44.  
    45.   signal clk1 : std_logic;
    46.   signal reset1 : std_logic;
    47.   signal counter:std_logic_vector(15 downto 0);
    48.  
    49.   begin
    50.       process
    51.         begin
    52.           if reset_z = '1' then
    53.           counter<="0000000000000000";
    54.           Q_z <= counter;
    55.         end if;
    56.         if (clk_z = '1') then
    57.           counter <= counter+'1';
    58.           Q_z<=counter;
    59.       end if;
    60.   end process;
    61.  
    62. end behavior;
    63.  = '1') then
    64.           counter <= counter+'1';
    65.           Q_z<=counter;
    66.       end if;
    67.   end process;
    68.  
    69. end behavior;
    70. [/COLOR]

    I think that the counter and clkAndReset working properly and the problem is that i can't pass the clk and reset from clkAndReset to counter.
    What do you think??
     
    Last edited: Nov 21, 2009
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