BCD-to-7 Segment decoder without ENABLE SSA

Discussion in 'Programmer's Corner' started by Murat Aslan, Apr 1, 2015.

  1. Murat Aslan

    Thread Starter New Member

    Mar 12, 2015
    14
    0
    I am going to have to have VHDL BCD-to-7 Segment decoder without ENABLE. I should add additional display like this
    additional ‘display’ output where:
    display <= not (input(1) and input(2) and input (3) and input(4));
    My code is here to check this.
    If it is false How can I add this(ssa)
    please check this.





    library ieee;
    use ieee.std_logic_1164.all;

    entity decodBCDto7seg_ssa is

    port( s:in std_logic_vector(3 downto 0);
    display:eek:ut std_logic;
    y:eek:ut std_logic_vector(6 downto 0));
    end decodBCDto7seg_ssa ;

    architecture sel of decodBCDto7seg_ssa is



    begin
    with s select
    y<= "0111111" WHEN "0000",--display 0
    "0000110" WHEN "0001",--display 1
    "1011011" WHEN "0010",--display 2
    "1001111" WHEN "0011",--display 3
    "1100110" WHEN "0100",--display 4
    "1101101" WHEN "0101",--display 5
    "1111100" WHEN "0110",--display 6
    "0000111" WHEN "0111",--display 7
    "0111111" WHEN "1000",--display 8
    "1101111" WHEN "1001",--display 9
    "0000000" WHEN others;

    display <= not (s(o) and s(1) and s(2) and s(3));
    end sel;
     
    Last edited: Apr 1, 2015
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