Hello,
I have written a code for a 115200 bps rate serial port adapt to 50 MHz clock (50MHz/115200*16) = 27.1267. That means that every 27 cycle a bit is sent, but as long as the number is not precise there might be some fluctuations after some cycles. Can you give me a tip on how to lets say implement a counter that counts serial port cycles and lets say after 8 of these cycles make a rate of 26 not 27 and then comes back to 27 again.
this is my code
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is port(C, CLR : in std_logic;
Q : out std_logic_vector(4 downto 0);
Z: out bit);
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(4 downto 0);
begin
process (C, CLR)
begin
if (CLR='1') then
tmp <= (others =>'0');
Z <= '0';
elsif (C'event and C='1') then
tmp <= tmp + 1;
Z <= '0';
if (tmp = "11011") then
tmp <= (others =>'0');
Z <= '1';
end if;
end if;
end process;
Q <= tmp;
end archi;
Thnx
I have written a code for a 115200 bps rate serial port adapt to 50 MHz clock (50MHz/115200*16) = 27.1267. That means that every 27 cycle a bit is sent, but as long as the number is not precise there might be some fluctuations after some cycles. Can you give me a tip on how to lets say implement a counter that counts serial port cycles and lets say after 8 of these cycles make a rate of 26 not 27 and then comes back to 27 again.
this is my code
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is port(C, CLR : in std_logic;
Q : out std_logic_vector(4 downto 0);
Z: out bit);
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(4 downto 0);
begin
process (C, CLR)
begin
if (CLR='1') then
tmp <= (others =>'0');
Z <= '0';
elsif (C'event and C='1') then
tmp <= tmp + 1;
Z <= '0';
if (tmp = "11011") then
tmp <= (others =>'0');
Z <= '1';
end if;
end if;
end process;
Q <= tmp;
end archi;
Thnx