basic PSpice problems

Discussion in 'Electronics Resources' started by funkpunk23, Jan 26, 2008.

  1. funkpunk23

    Thread Starter New Member

    Jan 26, 2008
    1
    0
    I'm trying to begin to understand basic circuit fragments, modelling them in PSpice and on my bread-board. I'm getting very weird, inconsistent results modelling really simple circuit fragments. I built a comparator with hysteresis yesterday that worked, and another today, that doesn't. The only obvious difference is that the poz and neg terminals on the op-amp are flipped. (yes, I tried flipping today's version around, and it still didn't work.)

    Why are these two ostensibly nearly identical schematics generating different netlists?

    Yesterday's netlist:

    *** INCLUDING 45e6-SCHEMATIC1.net ****
    * source 45E6
    E_U1 VOUT 0 VALUE {LIMIT(V(VPOZ,VINPUT)*1E6,-15V,+15V)}
    V_V1 VINPUT 0
    +PULSE -15 15 1m 2.5 2.5 1m 5
    R_R1 VPOZ VOUT 1k
    R_R2 0 VPOZ 1k

    **** RESUMING 45e6-schematic1-gyh.sim.cir ****
    .END

    WARNING -- Pulse Period < (Rise Time + Fall Time + Pulse Width) for V_V1
    WARNING -- Pulse Period < (Rise Time + Fall Time + Pulse Width) for V_V1

    JOB CONCLUDED

    TOTAL JOB TIME .02
    ****

    Today's netlist:

    **** INCLUDING comp2-SCHEMATIC1.net ****
    * source COMP2
    E_U1 0 0 VALUE {LIMIT(V(IN,0)*1E6,-15V,+15V)}
    R_R2 0 0 1k
    V_V1 IN 0
    +PULSE -15 15 1m 2.5 2.5 1m 5
    R_R1 0 0 1k

    **** RESUMING comp2-SCHEMATIC1-bbb.sim.cir ****
    .END

    ERROR -- Voltage source and/or inductor loop involving E_U1
    You may break the loop by adding a series resistance
    ******

    Any suggestions/insight would be *greatly* appreciated -- I feel like I'm banging my head against a wall before I can really even get started.

    Cheers,
    FP23.
     
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