Basic PLL loop operation

Thread Starter

domino89

Joined Sep 24, 2013
22
Hello
I was trying to understand operation of PLL in transient simulation. I have designed current starved ring oscilator which looks to work well but when I wanted to test the whole locked loop with XOR based phase detector it failed. It is far away from desired refrence clock. When i was debugging it I thought how it should actually work... XOR will give signal based on phase diffrence and this is filtered to give average stable value to drive ring osc. So when we get phase align phase detector will give 0 so ring oscilator will be off (since 0 volts will keep current source nMOS closed). Am I right?
 

Thread Starter

domino89

Joined Sep 24, 2013
22
Sry at the moment I can not post real schematic (i was making it in Cadence) But it is XOR, RC loop filter and VCO. I will post schematic as soon as I can (in like 3 days).
Best regards
 
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