basic logic gates

Discussion in 'General Electronics Chat' started by Gizachew worku, Feb 14, 2015.

  1. Gizachew worku

    Thread Starter New Member

    Jan 26, 2015
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    coud any one tell me, what would happen to the output of a two input AND gate if one input is feed high
    and the other is left open? What about an OR gate in the same situation??
     
  2. crutschow

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    Mar 14, 2008
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    It depends upon the logic family.
    In general, an open input is an undefined level and the output thus is also undefined.
     
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  3. kubeek

    AAC Fanatic!

    Sep 20, 2005
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    For some logic families like 74xx an unconnected input defaults to high. However CMOS variants like 74HCxx have very high input impedance, so the unconnected input will act like an antenna and can change its logic level even many thousands of times a second according to whatever stray electric and magnetic field happens to float in the surrounding area.
    Don´t take this such that with 74xx it is ok to leave pins unconnected, that is not true. They are a lot more immune to RF interference than CMOS, but definitely not bulletproof and will change state if sufficient energy comes along, like your neigbor turning on a large pump or something. Just allways connect unconnected inputs to a well defined level.
     
    Last edited: Feb 14, 2015
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  4. cmartinez

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    Jan 17, 2007
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    In a CMOS chip, a floating gate (a gate whose input is not tied high or low, and is simply left unconnected) is bad practice and can wreak havoc even on the other gates of the same chip that are properly connected. ALWAYS tie high or low an unused gate... common practice is to tie them low, that is, connect their inputs to ground. The outputs of those unused gates can be left floating.
     
  5. WBahn

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    Mar 31, 2012
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    A floating CMOS input can also cause a condition known as "shoot thru" where both the pullup and pulldown transistors in the output are turned on and current shoots through the device from power to ground, often destroying the device in the process. As already stated, always tie unused inputs to a defined level. For that AND gate you want to tie it HI and for that OR gate you want to tie it LO. Always leave unused outputs floating -- many people seem to think that because they need to tied unused inputs HI or LO that they must do the same with unused outputs.
     
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  6. cmartinez

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    Now that's interesting... is that distinction between AND and OR gates because that way current at the inputs would be held at a minimum in each case? Or is it just customary?
     
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  7. MrChips

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    That is because of the logic function. If you do the opposite then the gate serves to disable the input signal.
     
  8. ian field

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    With TTL; it would assume logic high level.

    CMOS has an extremely high resistance capacitive input, chances are a stray static charge could determine the logic level - which could drift.....very slowly.
     
  9. WBahn

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    If you tie one input of an AND gate LO, then the output is LO regardless of the other input. Similarly, if you tie one input of an OR gate HI, the output is HI regardless of the other input. Assuming you want the other signal to actually do something, you need to tie the unused input to a state that will not mask it. This situation would be more likely seen with a high-input gate such as a 5-input AND gate when you only needed a 4-input AND gate. It also applies when you have something like a FF that has Set and Clear inputs. If you don't need one or both of those, you need to tie them to whatever level prevents them from interfering with what you are doing. The same would be true on more complex logic functions like an up/down counter. If you only need an UP counter, then the control signal for the count direction needs to be tied to whatever level results in the counter counting up.
     
  10. WBahn

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    Not necessarily slowly. The change of state of any signal, including its own output, can cause enough coupling to floating input to change it's state resulting in feedback that causes the gate to oscillate at a very high rate.
     
  11. ian field

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    I generally clean the PCB after assembly to remove any extraneous leakage paths.
     
  12. cmartinez

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    I get it now. At first I was thinking about two-input gates, and in my mind I pictured a 74HC00 quad 2-input and gate chip... so what do I do with the unused gates? tie their inputs to ground of course. But it hadn't occurred to me that maybe the OP was talking about unused inputs of a gate with more than 2 inputs. So yes... unused AND inputs should be tied high, and OR inputs tied low, so as not to interfere with the result of the overall logic. Thanks.
     
  13. WBahn

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    Huh?

    How does that decouple an output signal that is capacitively coupled to a floating input signal? Think EMI.
     
  14. WBahn

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    To be a bit more specific to the original question as asked -- the scenario with the AND gate depends on whether it's TTL or CMOS. The scenario with the OR gate shouldn't matter since the one input that is HI will dictate the result. Still really bad design, though.
     
  15. Stuart Matthews

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    Oct 30, 2014
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    WBhan explained this very well except I would simply say tie the imputs according to their particular truth table. Example: an AND gate tie both inputs to low, an OR gate tie both imputs to low.
    Please feel free to correct me if I am wrong.
     
  16. MrChips

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    Proof read what you wrote and then correct your error.
     
  17. Stuart Matthews

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    Oct 30, 2014
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    Corrected, I was using my phone. Just edited with my PC, N & M should be kept apart from phone keyboards.

    WBhan explained this very well except I would simply say tie the inputs according to their particular truth table. Example: an AND gate tie both inputs to low, an OR gate tie both inputs to low.
    Please feel free to correct me if I am wrong.
     
  18. MrChips

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    You mean tie unused input of AND gate high.

    Tie unused input of OR gate low.
     
  19. Stuart Matthews

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    Oct 30, 2014
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    WBhan explained this very well except I would simply say tie the unused inputs according to their particular truth table. Example: an AND gate tie both unused inputs to low, an OR gate tie both unused inputs to low.
    Please feel free to correct me if I am wrong.
     
  20. Stuart Matthews

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    Oct 30, 2014
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    I have always tied unused inputs on an AND gate to low and on a NAND gate tie unused inputs to high.
    As I say according to the truth table of the particular gate.
    Why would you tie to high on an AND gate? As I see it it does not really matter as long as they are tied low or high, it is just my way of doing it to simplify things.
     
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