can somebody help me explain how the data "1" and "0" travel in this circuit or how data is being retained since it is a basic DRAM.

 

The word line is for selecting the RAM element to write to.

The bit line is for writing to/reading from the RAM element.

If you assert the word line, say the transistor is an nMOS device therefore '1' on the gate will 'open' the transistor, then the bit-line will equalise with the charge stored on the capacitor. If the bit-line is driven then you will write a value (either a '1' or '0') to the capacitor, and if the bit line is not driven then you will read the value from the capacitor, most probably using a current sense device.

If you de-assert the word-line, '0' on the transistor gate, then whatever the value (charge) stored on the capacitor will stay because it is now isolated. In reality the charge will leak away, hence why this RAM element is dynamic, i.e. it needs dynamically refreshing to retain the charge.

Hope that explains it a bit. If there is anything you don't understand let me know and I will try to make my explanation a little clearer.

Dave

 

thanks for the idea, i appreciate a lot. let me see if i understood it well. so, the bitline is where you input data (through the nMOS gate) and the wordline is accessed through the nMOS drain? please explain further if i didn't get it right. i'm new to memory circuits. tnx

 

thanks for the idea, i appreciate a lot. let me see if i understood it well. so, the bitline is where you input data (through the nMOS gate) and the wordline is accessed through the nMOS drain? please explain further if i didn't get it right. i'm new to memory circuits. tnx

Sadly, your not correct here. The bit line is where you both input data and read data from. The word line selects the RAM element you wish to write to or read from.

Take an example:

The capacitor initially has no charge stored on it, i.e. a value of '0'. We wish to write a '1' to the above RAM element. The following sequence of actions takes place to write to the RAM element:

1. We take the bit-line high, i.e. to '1'.
2. We assert the word-line, which for an nMOS device means we take the word-line high, i.e. to one.
3. When Vgs > Vth for the nMOS transistor the transistor opens and the capacitor begins to charge up from the bit-line.
4. Eventually the chage on the capacitor is equal to the charge on the bit-line - at this point we have written the value '1' to the RAM element.
5. To complete the write we de-assert the word-line. Now the charge stored on the capacitor is isolated and cannot leak away, i.e. '1' is stored on the capacitor (in reality it will experience leakage across the capacitor to ground, but that need not concern us at this point).

The following sequence of actions takes place to read from the RAM element:

1. We take the bit-line low.
2. We assert the word-line which opens the transistor.
3. If '0' is stored on the capacitor, the bit-line and capacitor charge are equalised, and the bit-line remains at '0' - we have read the value '0' from the RAM element.
4. If '1' is stored on the capacitor, the charge on the capacitor is greater than that on the bit-line and hence we will get a current flow from the capacitor to the bit-line, i.e. they are trying to equalise the charge. You can think of it as follows: the charge on the capacitor takes the bit-line to '1' - we have read the value '1' from the RAM element. (In reality the bit-line would not go to '1', and we would need a current sense to detect the current flow from the capacitor to the bit-line).

I know it probably seems a little difficult at this point. Look at my above explanation along side the diagram of the RAM element and walk through it step-by-step. Any more questions post back and I'll try to explain it.

Dave

 

Dave,

for sequence #3,

3. When Vgs > Vth for the nMOS transistor the transistor opens and the capacitor begins to charge up from the bit-line.

should this be:
3. When Vgs > Vth for the nMOS transistor the transistor close (current flows from drain to source) and the capacitor begins to charge up from the bit-line.

if that is the case, then i already understood it. please confirm

 

Dave,

for sequence #3,

3. When Vgs > Vth for the nMOS transistor the transistor opens and the capacitor begins to charge up from the bit-line.

should this be:
3. When Vgs > Vth for the nMOS transistor the transistor close (current flows from drain to source) and the capacitor begins to charge up from the bit-line.

if that is the case, then i already understood it. please confirm

When Vgs > Vth for the nMOS transistor, the transistor channel has an inversion layer (i.e. we say the transistor is open) and current flows from drain to source and the capacitor begins to charge up from the bit-line.

NB: If the transistor were closed there would be no inversion layer in the channel and current could not flow from drain to source.

Hope that clarifies a few things. Any further queries let me know.

Dave

 

thanks Dave! now i fully understood how the circuit works. we just didn't have the same protocol with regards to the terminology "open", now i know.
i find this site a lot informative and very helpful. thanks

 

thanks Dave! now i fully understood how the circuit works. we just didn't have the same protocol with regards to the terminology "open", now i know.
i find this site a lot informative and very helpful. thanks

Glad to be of help, any further problems let us know and we can try and help you out.

Dave