Hi,

I don't quite understand Output Impedence. For an interface/logic circuit that communicates via serial or something like that, how does Output Impedance effect the signal?

Thanks.

 

The effect is that as the loading increases, the voltage of the signal is attenuated within the source.
Think of a power supply which can be modeled with a internal series resistance Rs. As the current delivered to a load increases more current flows trough the series resistance Rs right ?. Ohm states that a voltage will be lost internally on this internal resistance. The effect is that as loading increases the voltage seen as delivered by the power supply (the source) is decreased (think of a voltage divider).

This applies similarly to any 2 parts of a circuit connected together which exhibit a output and input resistance towards each other. As the second part loads the preceding part further the higher is the "voltage drop" due to internal resistance in the preceding part. This is why low internal resistance is preferred in stages "sourcing" signals and high resistance in stages "sensing signals". These 2 parts form a "voltage divider".

Modeled as a voltage divider the second stage measures the signal over it's own input resistance. it is the lower resistor in this resistor divider "model". The sourcing stage is the upper resistor. From this you should realize that if the lower resistor is much bigger then the upper then the second stage will "sense" pretty much all of the signal voltage since most of the voltage falls over the second resistor. As we increase the upper resistance (source impedance) more voltage falls across it and the lower resistor "sees" less of the signal.

 

The effect is that as the loading increases, the voltage of the signal is attenuated within the source.
Think of a power supply which can be modeled with a internal series resistance Rs. As the current delivered to a load increases more current flows trough the series resistance Rs right ?. Ohm states that a voltage will be lost internally on this internal resistance. The effect is that as loading increases the voltage seen as delivered by the power supply (the source) is decreased (think of a voltage divider).

This applies similarly to any 2 parts of a circuit connected together which exhibit a output and input resistance towards each other. As the second part loads the preceding part further the higher is the "voltage drop" due to internal resistance in the preceding part. This is why low internal resistance is preferred in stages "sourcing" signals and high resistance in stages "sensing signals". These 2 parts form a "voltage divider".

Modeled as a voltage divider the second stage measures the signal over it's own input resistance. it is the lower resistor in this resistor divider "model". The sourcing stage is the upper resistor. From this you should realize that if the lower resistor is much bigger then the upper then the second stage will "sense" pretty much all of the signal voltage since most of the voltage falls over the second resistor. As we increase the upper resistance (source impedance) more voltage falls across it and the lower resistor "sees" less of the signal.

I appreciate the detailed response. I'll have to read it over. I'm still learning all of my definitions so I'm a bit lost.

Thanks.

 

In relation to your question about logic circuitry interfacing the notion of output impedance will be interpreted somewhat differently.

As steinar96 points out the loss of signal level at the point of interface is an important consideration. With logic circuits there is the consideration of the region of uncertainty between a logic "high" and logic "low" state. Generally logic circuits have a maximum 'fan-out' condition which must be satisfied for reliable circuit operation. Exceeding the fan-out limit for a particular logic type is not recommended. Also interfacing different logic types can have problems - CMOS and TTL for example.

At radio frequencies output impedance also requires additional considerations - say in relation to source/load mismatch, which potentially leads to signal level loss, wave reflections and other undesirable consequences.

 

So is there a rule of thumb as to whether the impedance should be large or small? The project we were shown in class was of a TTL to Serial circuit and it noted something about output impedance being affected by the value of the capacitors around the chip.

Not too hot with this logic jive. Sorry. And thank you very much.

 

Your question relates to TTL chip power supply decoupling. Decoupling via shunt capacitors (which is usually highly desirable if not essential) reduces the induced supply rail spikes inherent with TTL switching technology. Decoupling will also effectively lower the device output impedance - since the chip rail supply side source parasitic impedance will be bypassed to a certain extent.

A lower output impedance is probably desirable in most circumstances. However, as long as one knows what the impedance will be with a given design then the designer can take steps to reduce any detrimental effects.

 

Your question relates to TTL chip power supply decoupling. Decoupling via shunt capacitors (which is usually highly desirable if not essential) reduces the induced supply rail spikes inherent with TTL switching technology. Decoupling will also effectively lower the device output impedance - since the chip rail supply side source parasitic impedance will be bypassed to a certain extent.

A lower output impedance is probably desirable in most circumstances. However, as long as one knows what the impedance will be with a given design then the designer can take steps to reduce any detrimental effects.

Thanks a lot. I appreciate it.