Audio power amplifier analysis

Discussion in 'Homework Help' started by foolah44, Nov 14, 2012.

  1. foolah44

    Thread Starter New Member

    Nov 14, 2012
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    Hi,
    I have a pre-designed audio power amplifier to analyse and test. The circuit is attached.

    I have got several values but during test some of them were not quite right.

    My results
    __________

    differential (input) stage of about (-) 65.2 - that is for Q1
    second stage gain of about 1224 - that is for Q4
    feedback ratio, about 1/25 i.i 0.04
    Overall gain of about 26

    Input impedance of about 4.4KΩ
    Output impedance of less that 1Ω

    Low frequency limit of about 32Hz due to C2
    High frequency limit of about 133kHz due to C3


    at the output stage, we assume a load of 8Ω
    Maximum operational output voltage was about 3V peak (positive)

    which gave me an operational power delivered of about 0.56W

    Power supply is about 1W
    so effieciency gives me about 56%

    The maximum power dissipated at each output transistor was about 0.51W
    So heatsink not really needed.


    TESTING
    ________
    When testing my amplifier, The low and high frequencies limits were not right. I got about 25Hz and 4MHz for low and high frequency limits.

    Can you please help me check my results. Especially for high and low frequency limits, and also power analysis?
     
  2. Audioguru

    New Member

    Dec 20, 2007
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    The voltage divider of R5 and R6 create as voltage at point A of only 0.48V which is not enough to turn on Q3 and Q5 so the amplifier WILL NOT WORK.
     
  3. foolah44

    Thread Starter New Member

    Nov 14, 2012
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    With Vcc = 9V, the voltage divider of R5 and R6 creates a voltage of about 1.86V.

    The amplifier work.
     
  4. Jony130

    AAC Fanatic!

    Feb 17, 2009
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    Why you "skipped" C5?
    F1 = 0.16/(C2*R8) = 33Hz and F2 = 0.16/(C1*Rin) = 1.8Hz and F3= 0.16/(C5*RL) = 20Hz
    so the Fd ≈ 1.1 * √(F1^2 + F3^2) = 42Hz. Simulation in LTspice show similar result.
    And are you sure that in real life you use C2 = 22μF?
    Because if C2 >> 22uF then Fd approaching to F3= 0.16/(C5*RL) = 20Hz

    How do yo get this result? Maybe this is a open loop high frequency limit?
     
  5. foolah44

    Thread Starter New Member

    Nov 14, 2012
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    I used a 22uF, and I had about 25Hz when measuring on CRO.

    I got the high frequency by applying Miller's theorem on C3. But it gave me about 133kHz. Which is different from about 4.5MHz observed on CRO. I believe my approach was not right. Do you have a way to calculate the high frequency limit pls?
     
  6. Jony130

    AAC Fanatic!

    Feb 17, 2009
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    I need value of a β for the BJT that you used in your small signal analysis.
    Also what voltage you assume at R4 resistor maybe you assume 1V?
    As for Fd I don't know why you get 25Hz.
     
  7. foolah44

    Thread Starter New Member

    Nov 14, 2012
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    I used an hfe of 330 for all BC547/BC557.
    Voltage across is VA - Vbe = 1.86 - 0.7 = 1.06V.
     
  8. Jony130

    AAC Fanatic!

    Feb 17, 2009
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    Ok let's do some simplified approximation analysis.
    Input stage gain is equal to

    Av1 = (R3||rinQ4)/2re = (1.5K||1.2K)/14.85Ω = 666.666Ω/14.85Ω = 45[V/V] LTspice show 33[V/V]

    rinQ4 = (hfe + 1)*re4 = 331 * Vt/Ic = 331 * 26mV/7mA = 331 * 3.71Ω = 1.23KΩ

    2re = 4VT/Iee = 4*26mV/7mA = 14.85Ω

    Second stage (VAS) voltage gain is equal

    Av2 = (hfe+1*RL)/re4 = (91 *8Ω)/3.71Ω = 196[V/V] LTspice show 235[V/V]

    I assume hfe = 90 for BD139

    So the overall open loop gain is equal

    Aol = AV1 * AV2 = 8.82K [V/V] LTspice show 7.78K [V/V]

    Additional if we assume Cbe = 10pF and Cbc = 3pF we can find open loop roll-off frequency

    F = 0.16/ ( R3||rin4 * (cbe + Av2*(cbc+C4) ) ) = 0.16/(666.7 *9.86nF) = 24.3KHz
    And gain bandwidth product is equal to

    GBP = 8.82K * 24.3KHz = 214MHz 71MHz in LTspice

    So if close loop gain is equal to 1+R7/R8 = 26.5 the high frequency cut-off is equal to Fc = 214MHz/26.5 = 8MHz LTspice show 5.6MHz

    As you can see our calculations are as good as our model we used.
    And this is why in real life we add additional capacitor+resistor to ensure and clearly determine high frequency cut-off.
     
    Last edited: Nov 16, 2012
    foolah44 likes this.
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