I'm using AT91SAM7X256 development kit.
This thread regards the AIC & PIT.

Some weird behavior of interrupts: they are triggered every time that an interrupt handler has been executed, only when the PIT_MR PIV field is lower than 8.

The actions I made and the results are as follows:

1. Reading PIT_PIVR and thus acknowledging any existing interrupt (if exists), which resets PICNT and clears the PITS bit.
2. Configuring PIT:
   
   In PIT_MR register:
   1. PIV = 6
   2. PITEN = 1
   3. PITIEN = 1
   
   
3. Configuring AIC:
   1. Configuring interrupt properties for SYSC (peripheral id=1) such as: interrupt level, interrupt triggering condition (on high level), a handler.
   2. Enabling interrupts for SYSC.
   3. Clearing interrupt for SYSC. (thus acknowledging any pending interrupt)
   
   
4. Immediately after clearing interrupt for SYSC, the processor jumps & executes the handler.
5. Immediately after the handler execution has ended, the processor executes the following ASM code which is located in the startup.s file:
   
   
   LDR pc, #-0xF20
6. Immediately after that, the processor executes the handler again.

The last 3 actions are executed again and again, which is a wrong behavior.
I expect that the processor would perform another task between every interrupt, but it seems that the interrupt is triggered immediately after the handler has been executed.

Have you encountered this problem?
ANY suggestions?

BTW, inside the handler I acknowledge the interrupt of course.

Thanks in advance.

Regards,
Dor.

 

What clock are you running?

How long is a PIV of 6 going to take before it is supposed to interrupt the system?

A 48MHz clock would take a PIV of 3000 for a milliseconds interval.

 

The oscillator (18.432MHz) is my MCK. (master clock)

Thus when PIV=1, the interval is approx. 1us (one micro-second).

There's enough time to execute other stuff in each interval.