Astable Multivibrator - How does it work?

Discussion in 'General Electronics Chat' started by bd525, Dec 30, 2009.

  1. bd525

    Thread Starter New Member

    Nov 11, 2009
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    I am trying to understand the workings of a astable multivibrator, everytime I think I got how it works I find explanation that makes me think I dont know jack...

    Would any one be willing to walk me through the process from power on through the state changes of the diagram I have attached? I have really tried to research this on my own but I feel I am not getting anywhere.
     
  2. hgmjr

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  3. Wendy

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    You have two inverters back to back, coupled through the capacitors. It is possible if everything is perfectly balanced the circuit will freeze, however normal variation makes this highly unlikely.

    So each half of the square wave depends on the RC constant feeding the inverter (R3,C2 and R2,C1). When the capacitor is charged the inverter feeding it turns off, causing the other inverter to flip state.

    Here's Wikipedia's take...

    http://en.wikipedia.org/wiki/Multivibrator

    ***

    Heh, you beat me this time...
     
  4. bd525

    Thread Starter New Member

    Nov 11, 2009
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    I have read this, but I am unclear about what happens to the cap attached to a transistor collector who just went into the "off" state.... does it discharge then start charging again? I guess I am having touble visualizing the flow of electrons when these states change... and the voltages a cetain points in the circuit when states change.
     
  5. bertus

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  6. hgmjr

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    The signal at the collector of the transistor that just turned on, is AC coupled to the base of the other transistor temporarily turning the other transistor off.

    The capacitor eventually discharges which then turns the other transistor on setting up the circuit to switch states.

    hgmjr
     
  7. bd525

    Thread Starter New Member

    Nov 11, 2009
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    bertus, I am going to be checking that link as soon as I can get to a machine to do so...

    hgmjr, when you say AC coupled is in realtion to how the capitor reacts to changes in voltage?
     
  8. bd525

    Thread Starter New Member

    Nov 11, 2009
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    bertus, that link help me visualize whats going on much better!!! Thanks!!

    the link made this statment, "As the collector current into Q1 charges C1, the base voltage for Q2 goes up, until it is high enough to switch on Q2, causing a current to flow through its collector, which drops the collector voltage (the current causes a voltage drop across the resistor above it). The right side of C2 has dropped, but the voltage across it hasn't changed, so this causes Q1's base voltage to drop below ground, switching it off. "

    I think a part of my confusion is coming from the part that says "but the voltage across it hasnt changed" in reference to C2 what is happeing here? I may be making this harder than it needs to be... Have I forgotten something about capacitors (or maybe didtn understand it in the first place)?

    BTW the drawing I posted is the same as the one in page link posted by bertus but with animation.
     
  9. Jony130

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    Feb 17, 2009
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    We assume that Q1 in ON and Q2 is OFF.
    So C2 is charging through
    Vcc-->R4--->C2--->base-emiter Q1-->gnd
    So when C2 stop charged the voltage on capacitor is equal Vcc-Vbe=8.4V
    But Q1 is still ON thanks to R3.
    And now Q2 is ON (in saturation), Saturated Q2 shorts right plate of C2 to GND. So voltage on base Q1 will by -8.4V because charged capacitor act as a voltage source.
    [​IMG]



    So Q1 will by cut-off and C1 is charged (Vcc-->R1---C1--->base-emitter Q2--->GND).
    Now C2 wile be discharge through
    Vcc-->R3---C2-->colector-emiter Q2--->gnd.
    Discharge ends when voltage on C2 riches 0V but now C2 in now start charging in the same direction
    Vcc-->R3---C2-->colector-emiter Q2--->gnd.
    And this means that voltage on C2 is start to rise in opposite direction.
    [​IMG]
    So when voltage on C2 increase to 0.6V the Q1 will be start to open.
    Q1 open means that C1 ( charged in the previous cycle to 8.4V) immediately cut-off Q2.
    So we back to the beginning when Q1 is open.
     
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  10. bd525

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    Nov 11, 2009
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    Jony130, Very helpful!!! I am going to read it about 30 times but I think I got it with your explanation! I may have question or 2 about the explanation as I wrap my head around later this evening when I get a chance to study it.
     
  11. Jony130

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    My English is poor, but maybe you will understand something.
     
  12. Jony130

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    Assuming that C1 is not initially charged and Q1 is ON so Q2 must be OFF since voltage on C1 is 0V (empty capacitor act like short-circuit) and Q1 is in saturation (Vce≈0V)
    [​IMG]


    So voltage on base Q2 is near 0V and that why Q2 is cut-off.
    C2 is quickly charge to 8.4V through:
    Vcc-->R4--->C2--->base-emiter Q1-->gnd (blue line)

    But Q1 is still on saturation thanks to R3 (purple line)

    And C1 begins to charge through
    Vcc-->R2-->C1-->collector-emitter Q1--->gnd (red line)
    When voltages on C1 reach 0.6V Q2 is now begins to open.
    Opening Q2 means that voltage on collector Q2 start to drop.
    Since capacitor C2 has been previously charged to the voltage around 8.4V. This voltage on C2 cannot suddenly change (charged capacitor act as a voltage source), so when the collector voltage of Q2 and "positive" electrode of C1 drops to zero, the "negative" plate of C1 decrease below the GND to -8.4V. So voltage on Q1 base becomes negative -8.4V, and that cut-off Q1. Voltage on the collector (which had previously been close to zero) increases, but not immediately.
    [​IMG]

    Rapid shut-down of Q1 allow current to flow through:
    Vcc-->R1-->C1-->base-emitter Q2-->gnd (red line)
    This current surely full open Q2 and full charged the C1 to 8.4V.
    But Q2 is remain open because its base current will be flow through R2.(blue line)
    This situation will continue until the voltage on the base of Q1 will increase to about 0.6V and Q1 is start to open. This will be start in time determine by R3 and C2.
    As mentioned earlier, when the voltage on the collector Q2 fell to ground, and a charged capacitor C2 "pulled down" the voltage at base Q1 below gnd (-8.4V), but this state will not last long. The discharge current will be flow through
    Vcc-->R3-->C2-->colector-emiter Q2-->gnd (purple line)
    Voltage on the "negative" plate of C2 is rising (voltage become more positive) at some point becomes equal to zero (end of discharge), and will continue to grow (C2 is now charging, purple + and - on diagram).
    When voltage on C2 rises to about 0.6V the Q1 is start to open.
    So voltage on Q1 collector is start to drop so that previously C1 charged to 8.4V "pulls-down" the voltage on the base of Q2 below gnd (-8.4V) so Q2 will be immediately cut-off.
    C2 quickly recharges through R4 and C1 is slowly discharged through R2 and voltage on the base of Q2 will gradually grow from negative values(-8.4V) ,through zero to 0.6V so Q2 in start to open and the whole game start repeated itself.
    So for proper operation of this circuit R2 and R3 must be much larger then R1, R4.
    [​IMG]
     
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  13. bd525

    Thread Starter New Member

    Nov 11, 2009
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    Jony130,

    Your first explanation was great and cleared up a lot. I am going to read through and study your second explanation as soon as I get a break at work... from what I see so far with all the detail you put in I think it will handle all my questions.

    BTW your english seems pretty good to me.

    I will let you know as soon as I get a chance.
    Thanks!
     
  14. Audioguru

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    Dec 20, 2007
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    Most little silicon transistors have a max allowed reverse-bias voltage from emitter to base of only 5V to 6V. Jony's circuit has 8.4V which will cause the transistor emitter-base junctions to have avalanche breakdown which slowly destroys the transistors and spoils the timing of the circuit. Therefore the max supply voltage is 5.3V unless diodes are added.
     
  15. hgmjr

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    Jan 28, 2005
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    As Audioguru has pointed out, application of excessive reverse-bias voltages to the base-emitter junction is a real and present danger to the BJT transistors. The damage is not immediately evident but with time the transistors will incur irreversible damage. The primary degradation mode is the decrease in the beta of the transistors.

    As he suggested, lowering the power supply voltage used to power the circuit is probably the simpliest method of addressing the problem.

    hgmjr
     
  16. Jony130

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    Feb 17, 2009
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    Long time ago I measure reverse-bias voltage from emitter to base and emitter to collector in general purpose BJT
    [​IMG]

    For PNP

    BC556
    Vbe=10V; Uce=10.65V

    BD140

    Ube=12.55V ; Uce=13.02V


    And for NPN
    BC337-40
    Veb=8.2V; Vec=6.7V; I=5.5mA

    BC549B

    Veb=8.3V; Vec=7.2V; I=5.5mA

    BD139-16

    Veb=8.5V; Vec=6.7V; I=5.5mA

    BC639

    Vbe=7.7V; Vec=6.3V; I=500uA

    BC337
    Veb=7.9V; Vec=6,4V; I=500uA

    2SC945
    Veb=8.1V; Vec=7,5V; I=500uA

    And of course it's possible to create simple generator using reverse-bias emitter-collector junction.
    http://www.cappels.org/dproj/simplest_LED_flasher/Simplest_LED_Flasher_Circuit.html
     
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  17. Audioguru

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    Hi Jony,
    Your numbers are mixed up.
    The emitter to collector voltage should be higher than the emitter to base voltage because it is the emitter to base voltage plus the 0.65V forward-biased collector base junction in series.
     
  18. Jony130

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    Well, I was also surprised by the results, but for sure results a 100% correct.
    Checkout yourself.
     
  19. Audioguru

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    Your numbers are mixed up.
    They should be like this:
     
  20. Jony130

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    Numbers are OK.
    Only for PNP Vec is 0.6V greater then Veb
    For NPN Vec is smaller then Veb.
    If you don't believe my measurements do the measurement yourself.
     
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