Another DIY LDO regulator... discretely!

Discussion in 'The Projects Forum' started by Gaudeamos, Jun 29, 2013.

  1. Gaudeamos

    Thread Starter New Member

    Jun 24, 2013
    15
    2
    I've breadboarded this LDO design that I have sketched in my notes from a few years ago. It's an LDO circuit consisting solely of discrete components. I'm sure that I copied it from some www page, but I can't find that source now. In fact, recently I haven't found any discrete LDO design not involving an opamp. I've attached the schematic and LTSPICE model.

    I'm new to this (or any) forum, so I'll be as brief as possible in this opening posting, and fill in the blanks as requested. I'm hoping to attract constructive feedback from this community that will help me move forward. I'll post more specific questions subsequently.

    I intend to integrate this design around a FET load switch that's already committed to the design. These are my goals for this circuit:

    - Output below 10V with input <=15V @ 2-3uA for standby operation, 10-25mA for normal operation. Precision is not crucial.

    - Teeny dropout: As overvoltage represents an abnormal condition, I want the regulator to have minimal effect on the power supply when operating normally. Ie I'm looking for ZERO additional effect to the open switch that's already in the design. The FET (VP3203; Rdson=1R0) drops about 10mV in normal operation.

    - Miserly power requirement: I'm aiming for 10uA max when not regulating, and not much more when supplying the (dormant) standby curcuit (requires 2-3uA; 2uF capacitance). So far I've got it down to 21uA.

    - The components requiring overvoltage protection:
    A 3V regulator powering the standby circuit (MCP1702-3.0); can take 13Vmax.
    A couple of Al-lyte caps rated at 10V. I know, I shouldn't be cutting cap voltage tolerances that close, but let's just go with this requirement for academic reasons.

    - The load circuit requires 10-20mA clean enough not to cause audible power supply hum. The Load has capacitance of around 350uF.

    The attached files represent the current state, after several iterations using lower resistor values. As I increase resistor values to bring down the quiescent current, I'm finding the circuit to be increasingly sensitive to internal detail and to its environment. I get the feeling that this is par for LDO regulators.

    I'm having a bit of a problem with the SPICE model: It's set up to simulate first powering the standby circuit, and subseqently the application. I've tweeked the model to behave reasonably well for this scenario. However, when I configure both standby and application circuits to power up simultaneously (by bypassing S2), the model ends up with unstable (oscillating) output. My gut tells me that this is due to an imperfection in the model... Of course my breadboard version behaves consistantly regardless of the order of powering up.

    Note that I don't own a scope... I have only my DVM (and an analog one) and the backend application circuit to assess my LDO circuit. The output measures a consistent 9.7V (pretty close to the expected theoretical result), and I can hear no power supply hum (the application is a portable headphone amplifier).

    I'll leave it at that for this original post. Please feel free to ask me for any clarifications, ellaborations, explanations, etc...

    thanks in advance
    :D <sigh> that was brief, wasn't it??
     
  2. Ron H

    AAC Fanatic!

    Apr 14, 2005
    7,050
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    It's not clear to me that your post has any questions.:confused:
    I stopped the oscillations at the Q2 collector (in simulation) by adding 100pF from base to collector on Q1.
     
  3. Gaudeamos

    Thread Starter New Member

    Jun 24, 2013
    15
    2
    Thanks Ron H. Your change nicely stabilizes the transient response of the regulator.

    Given the observed oscillation at Q2 collector/M1 base, how did you determine the placement and value of the added cap? I'd like to get a better handle on the thought process for tuning such a circuit... looking for an improvement on my try-and-see approach.

    Now, here's what really perplexes me about this sim model: when the entire circuit is powered at once (by wiring S2 closed; file attached), the response is very much unstable, and does not stabilize. Is this possible in the real world? I mean, can a control system's response to a given state depend on the sequence of changes leading to that state? btw the additional cap that you suggested doubled the amplitude of these oscillations.
     
  4. bountyhunter

    Well-Known Member

    Sep 7, 2009
    2,498
    507
    I recommend you build one up on a proto board and see. It's low power, easy to do, and will let you see what it actually does. You test stability by "load stepping" a load resistor on the output to get a step change in load current.
     
  5. Gaudeamos

    Thread Starter New Member

    Jun 24, 2013
    15
    2
    Thanks for the suggestion bountyhunter... been working on that.

    This specific scenario would not really apply to my 'real-life' circuit anyways; the load powers up softly to limit initial inrush. I'm just wondering about the SPICE model's behaviour, trying to get an idea on how much to trust its validity.
     
  6. LDC3

    Active Member

    Apr 27, 2013
    920
    160
    You can try adding a choke to your simulator to slow the inrush of current.
     
  7. Ron H

    AAC Fanatic!

    Apr 14, 2005
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    Guadeamos, I haven't answered your last question for me because, during subsequent sims with another compensation scheme, I ran into a transient that occurred on the output when the voltage source powered up (before the master power switch was turned on). Could that cause a problem?
     
  8. Gaudeamos

    Thread Starter New Member

    Jun 24, 2013
    15
    2
    You mean the little surge on startup that leaves about 3.5V worth of charge trapped at node VSB? I was wondering about that myself. I assumed that it was unrelated to instability after switching.

    I've been trying to get to the bottom of the startup transient since my last post, The FET gate voltage ramps up at a slightly lower rate than the supply (first 20 microsecs). That difference opens M1 momentarily. There's some current going thru R2, Q2 collector to base during that time. Can that be a transistor shutoff transient? At what point do you start questioning the validity of the component models?

    I got a slight improvement by bypassing R3 with a diode (pointing north). The idea was to speed up FET shutoff. Now node VSB is charging to 2V. I'm still not happy about the transient.
     
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