Ancient hardware challenge:Reading parallel EEPROM from PIC16 chip

Discussion in 'Embedded Systems and Microcontrollers' started by korchoi, Jun 27, 2015.

  1. korchoi

    Thread Starter Member

    Jun 5, 2015
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    6
    Hello, dear Forum dwellers. Here i am with a situation that should get your minds working.
    If you are like me and prefer concrete problem solving over theorical abstract questions, here is a Nice challenge for you:
    I have all these EEPROM's from some old karaoke machine PCB's(those that would read your voice over a MIDI track.Old times).Also got some SRAM.
    If the static from the Plastic supermarket bag has not already killed them all, i should be able to work with 128KB of ROM from the AT49F010 chips.
    The AT49F010 is Written through a "Clear entire chip" data write sequence and then through Setting the selected bytes of each address.
    So here is the Challenge:
    A PIC16F628A or 16F877 has to access external memory for sizeable data. But there is no External data and memory bus, just byte-sized GPIO PORT's.
    Extend two GPIO ports into a 16-bit address bus and an 8-bit data bus with chip select for 2 peripherals. Bonus points doing this with a single port.
    Restrict the external to 74xx series glue logic. Restrict circuit size to two breadboards. Bonus points for fitting on a single breadboard.

    Now that i am thinking further about it, it will be quite slow to access external peripherals with software defined multiplexed busses.
    Doing that on a single breadboard seems fantasiously optimistic.
    Here is my take:
    Two bytes on ram will be treated as a single int(16-bit) type, which will be the external address bus.
    One byte will contain the chip select combination and read-write bit. Another byte will contain the data bus value.
    So, two pins will each chip-select one Byte-sized address latch and another 4 pins will select the external peripherals.
    With that, i only use 2 latches for external output and The data bus doubles as an address bus!
    The problem is that the access cycle will be longer than with a hardware based bus(select latch, write latch, select latch, write latch, select chip, read/write chip.)
    bit 7 of the command bus will be read/write pin.
    Here is a picture so you don't get lost: WP_20150627_16_57_32_Pro.jpg
     
  2. nsaspook

    AAC Fanatic!

    Aug 27, 2009
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  3. korchoi

    Thread Starter Member

    Jun 5, 2015
    59
    6
    uC selection is limited to the 16f628A and the 16F877. The 16f628A has no parallel port and the 877 only works as an 8-bit slave.
    I am trying to implement a 16-bit parallel master.
    PS. your picture is all black...
     
  4. nsaspook

    AAC Fanatic!

    Aug 27, 2009
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    The 'picture' is a youtube video from Microchip. I might take a SPI serial to parallel converter approach to the EEPROM read problem with a single port. Clock out the address on one 16bit output shift register, then clock in the data on a 8 bit read shift register.
     
  5. korchoi

    Thread Starter Member

    Jun 5, 2015
    59
    6
    I could bypass the data straight into a fully free 8bit port. So just one 16 bit output. two octal D flip-flops and the task is up. an extra flip-flop will complete 128KB.
     
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