Analyzing a CMOS NAND gate

Discussion in 'Homework Help' started by thebomb, Apr 6, 2016.

  1. thebomb

    Thread Starter New Member

    Mar 16, 2016
    3
    0
    Hi everyone,

    My textbook has an example NAND gate:
    Screenshot from 2016-04-06 15-25-01.png
    and it says the following:
    The problem is that I can't figure out why P2 is ON. To me both P1 and P2 are connected directly to A so they should both be OFF.

    Can you tell me what's wrong with my reasoning?

    Thanks
     
  2. Jony130

    AAC Fanatic!

    Feb 17, 2009
    3,957
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    No, P1 gate is connected to point A and P2 gate is connected with point B.
     
  3. thebomb

    Thread Starter New Member

    Mar 16, 2016
    3
    0
    Can you explain why?

    Edit: scratch that, it just hit me
     
  4. Jony130

    AAC Fanatic!

    Feb 17, 2009
    3,957
    1,097
    Simply they forget about the "dot" convention
    01048.png


    S1.png
     
  5. crutschow

    Expert

    Mar 14, 2008
    13,028
    3,237
    Normally a "T" junction is considered to be a connection, but I prefer to always use dots.
     
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