analysis in cmos

Discussion in 'General Electronics Chat' started by vead, Apr 25, 2014.

  1. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    I want to need some help in the area of analysis in coms circuit

    transient analysis
    Dc analysis

    Dc analysis - we can know required dc voltage and current
    transient analysis -we can know the raise time, fall time

    analysis for component
    dc voltage
    dc current
    fall time
    raise time

    analysis for circuit
    dc voltage
    dc current
    fall time
    raise time

    1)Is it correct way ?


    I am going to design cmos inverter on simulator



    2)what will be ideal value for cmos inverter ?

    I mean rise time , fall time, length, width for nmos and pmos



    3) If input voltage is 3.3 what will be output voltage ?
     
  2. tshuck

    Well-Known Member

    Oct 18, 2012
    3,531
    675
    Is what the correct way?:confused:



    Ideally 0.


    3.3V.
     
  3. bertus

    Administrator

    Apr 5, 2008
    15,652
    2,348
    Last edited: Apr 25, 2014
  4. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    But its not possible in real circuit
    what should be good characteristic for cmos circuit
    1)It should be dissipate less power
    2)It should have zero propagation dealy
    3)should have noise immunity
    4)rise time and fall time should be less
    does anyone know another specification ?
     
    Last edited: Apr 25, 2014
Loading...