Analyse a comparator

Discussion in 'General Electronics Chat' started by screen1988, Jun 20, 2013.

  1. screen1988

    Thread Starter Member

    Mar 7, 2013
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    Hi,
    Can anyone tell me how can I analyse this comparator?
    [​IMG]
    [​IMG]
    I need some guides on how to start figure how this work and why they are connected like that.
     
  2. WBahn

    Moderator

    Mar 31, 2012
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    Consider the case when the inputs are equal. What will the output be (and don't be afraid to be qualitative). Then ask yourself what chain of events happens if one of the inputs is increased and how does that affect the output. Then ask the same question but for the case when that input is decreased.
     
  3. screen1988

    Thread Starter Member

    Mar 7, 2013
    310
    3
    If inputs are equal, Vout will be maximum! But I can't explain it.
    If Vplus = Vminis => Id1 = Id2
    The top part looks like an PMOS mirror current. I can figure out Vgs of P1 and P2 based on Id1 or Id2 but get stuck in finding Vout.
    Any more hint?
     
  4. WBahn

    Moderator

    Mar 31, 2012
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    Yes, the PFETs form a current mirror.

    Why are you saying that Vout will be a maximum? I realize you saying you can't explain why, but what is the reason you are making the claim at all, then.

    In your simulation, what is Vin? Your schematic has Vplus and Vminus.

    If you can describe the voltage at the junction of the left two FETs for the case when Vplus=Vminus, then what would symmetry say about the voltage at the junction of the right two FETs?
     
  5. screen1988

    Thread Starter Member

    Mar 7, 2013
    310
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    I meant saturation voltage.
    Vin is a sinusoidal signal with an offset of 0.5V. In this case Vin is connected to inverting input Vminus and a continuous signal Vseuil=0.5V is connected to non-inverting input Vplus.
    But I don't see this is symmetric. P1 has D and G connected together but P2 doesn't.
    How can I calculate Vout?
     
  6. WBahn

    Moderator

    Mar 31, 2012
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    Saturation voltage of what? Why do you think whatever it is you are referring to is saturated?

    Knowing that is somewhat important to understanding what your plot is telling us, isn't it? Why make us guess?

    So? If the two inputs are identical, why would that matter?

    Look at just the left hand pair. The input Vplus sets a particular Vgs on the NGET which wants to allow a certain current to flow from drain to source. The PFET is a diode connected FET and the voltage at the junction of the two FET drains directly establishes the Vgs value for the PFET. As that node voltage goes up the current in the NFET increases and the current in the PFET increases while as the node voltage goes down the reverse happens. The end result is that the voltage on that node settles at whatever value is needed to result in the same current flowing through both FETs.

    Now look at the other side. It has the same Vgs on the NFET as the left side and has the same Vgs on the PFET as the right side. How could it NOT have the same current as the left side and the same voltage at the junction of the two FETs as the left side (assuming no loading on Vout)? You should be able to satisfy yourself that this is the ONLY voltage on that node that will allow the two FETs to carry the same current, which they have to since they are in series.

    Another way to look at it would be to diode connect both PFETs but don't hook the two gates together. It it then obvious that the two gate voltages, though not connected, would be at the same voltage?

    If so, then imagine connecting the gate voltages. Since they are already at the same voltage, nothing changes, right?

    Now imagine cutting the connection between gate and drain on the right PFET. Since the gate of that PFET is being held at the same voltage by the same thing that is holding the gate of the other PFET at that voltage, nothing changes, right?

    To actually calculate Vout you need to know the model parameters for the FETs, but what, roughly, will be the voltage at the junction of the two FETs on the left side?
     
  7. Jony130

    AAC Fanatic!

    Feb 17, 2009
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    Do you know how differential amplifier work?
    Because the circuit you post is nothing more than a MOSFET differential amplifier with active load.
    Or maybe I should say behave in very similar way.
     
    Last edited: Jun 21, 2013
  8. WBahn

    Moderator

    Mar 31, 2012
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    Yeah. Similar but different. Without a current source this has horrible commom-mode rejection. But most of the concepts apply fairly readily.
     
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